DDR3
ECC MINI-UDIMM
MODULE CONFIGURATIONS
Viking Part Number
Capacity
Module
Configuration
Device
Configuration
Device
Package
Module
Ranks
Performance
CAS Latency
VR7JU567258FBZ
VR7JU567258FBA
VR7JU567258FBB
VR7JU567258FBC
VR7JU567258FBD
VR7JU567258FBE
VR7JU127258GBZ
VR7JU127258GBA
VR7JU127258GBB
VR7JU127258GBC
VR7JU127258GBD
VR7JU127258GBE
2GB
2GB
2GB
2GB
2GB
2GB
4GB
4GB
4GB
4GB
4GB
4GB
256Mx72
256Mx72
256Mx72
256Mx72
256Mx72
256Mx72
512Mx72
512Mx72
512Mx72
512Mx72
512Mx72
512Mx72
128Mx8
128Mx8
128Mx8
128Mx8
128Mx8
128Mx8
256Mx8
256Mx8
256Mx8
256Mx8
256Mx8
256Mx8
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
FBGA
2
2
2
2
2
2
2
2
2
2
2
2
PC3-6400
PC3-8500
PC3-8500
PC3-10600
PC3-10600
PC3-10600
PC3-6400
PC3-8500
PC3-8500
PC3-10600
PC3-10600
PC3-10600
CL6 (6-6-6)
CL7 (7-7-7)
CL8 (8-8-8)
CL8 (8-8-8)
CL9 (9-9-9)
CL10 (10-10-10)
CL6 (6-6-6)
CL7 (7-7-7)
CL8 (8-8-8)
CL8 (8-8-8)
CL9 (9-9-9)
CL10 (10-10-10)
Features
•
•
•
•
•
•
JEDEC standard 1.5V ± 0.075V Power Supply
o
VDD = 1.5V ±0.075V
o
VDDSPD = +3.0V to +3.6V
244pin Mini Unbuffered Dual-In-Line Memory Module.
8 Internal Banks.
Programmable CAS Latency: 6, 7, 8, 9, 10
Programmable CAS Write Latency (CWL).
Programmable Additive Latency (Posted CAS).
•
•
•
•
•
•
•
Fixed burst chop (BC) of 4 and burst length (BL) of 8 via
the mode register set (MRS)
Selectable BC4 or BL8 on-the-fly (OTF)
On-Die-Termination (ODT) and Dynamic ODT for improved
signal integrity.
Refresh. Self Refresh and Power Down Modes.
Serial Presence Detect with EEPROM.
On-DIMM Thermal Sensor.
RoHS Compliant* (see last page)
Nomenclature
Module Standard
PC3-6400
PC3 -8500
PC3-10600
SDRAM Standard
DDR3-800
DDR3-1066
DDR3-1333
Clock
400MHz
533MHz
667MHz
Viking Modular Solutions♦20091 Ellipse♦Foothill Ranch, CA 92610
Tel (800) 338-2361 Fax (949) 666-8159♦Website: http://www.vikingmodular.com
This Data Sheet is subject to change without notice.
Doc. # PS7JUxx7258xxx-LF Revision A1 Created By: Brian Ouellette
Page 1 of 19
DDR3
ECC MINI-UDIMM
PIN CONFIGURATIONS
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Front Side
VTT, NC
VREFDQ
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
Pin
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
Back Side
VTT, NC
VSS
DQ4
DQ5
VSS
DM0,DQS9,
TDQS9
NC,DQS9#,
TDQS9#
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1,DQS10,
TDQS10
NC,DQS10#,
TDQS10#
VSS
DQ14
DQ15
VSS
DQ20
DQ21
Pin Front Side Pin
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
DQ25
VSS
DQS3#
DQS3
VSS
DQ26
DQ27
VSS
CB0
CB1
VSS
DQS8#
DQS8
VSS
CB2
CB3
VSS
RFU
RESET#
CKE0
VDD
BA2
NC
VDD
A11
A7
VDD
A5
A4
VDD
A2
154
Back Side
Pin Front Side Pin
63
64
65
VDD
NC, CK1
NC, CK1#
185
186
187
KEY
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
VDD
VREFCA
VDD
NC
VDD
A10 / AP
BA0
VDD
WE#
CAS#
VDD
S1#, NC
ODT1, NC
VDD
S2#, NC
RFU
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
VDD
VDD
EVENT#
A0
VDD
BA1
VDD
RAS#
S0#
VDD
ODT0
A13
VDD
S3#, NC
RFU
VSS
DQ36
DQ37
VSS
DM4,DQS13,
TDQS13
NC,DQS13#,
TDQS13#
VSS
DQ38
DQ39
VSS
DQ44
Back Side
VDD
CK0
CK0#
Pin Front Side Pin
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
DQ40
DQ41
VSS
DQS5#
DQS5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DQS7#
DQS7
VSS
DQ58
DQ59
VSS
SA0
SCL
SA2
VTT
214
215
216
Back Side
DQ45
VSS
VSS
DM3,DQS12,
155
TDQS12
NC,DQS12#,
156
TDQS12#
157
158
159
160
161
162
163
VSS
DQ30
DQ31
VSS
DM5,DQS14,
TDQS14
NC, DQS14#,
217
TDQS14#
218
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
219
220
221
222
223
224
225
CB4
CB5
VSS
DM8,DQS17,
164
TDQS17
NC,DQS17#,
165
TDQS17#
166
VSS
CB6
CB7
VSS
RFU
NC(TEST)
CKE1, NC
VDD
A15, NC
A14
VDD
A12 / BC#
A9
VDD
A8
A6
VDD
A3
A1
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
DM6,DQS15,
TDQS15
NC,DQS15#,
226
TDQS15#
227
VSS
DQ54
DQ55
228
229
230
231
232
233
VSS
54
DM2,DQS11,
146
55
TDQS11
NC,DQS11#,
147
56
TDQS11#
148
149
150
151
152
153
VSS
DQ22
DQ23
VSS
DQ28
DQ29
57
58
59
60
61
62
VSS
DQ60
DQ61
VSS
DM7,DQS16,
234
TDQS16
NC,DQS16#,
235
TDQS16#
236
VSS
DQ62
DQ63
VSS
VDDSPD
SA1
SDA
VSS
VTT
237
238
239
240
241
242
243
244
Viking Modular Solutions♦20091 Ellipse♦Foothill Ranch, CA 92610
Tel (800) 338-2361 Fax (949) 666-8159♦Website: http://www.vikingmodular.com
This Data Sheet is subject to change without notice.
Doc. # PS7JUxx7258xxx-LF Revision A1 Created By: Brian Ouellette
Page 2 of 19
DDR3
ECC MINI-UDIMM
PIN FUNCTION DESCRIPTION
SYMBOL
CK0
CK0#
CKE[1:0]
TYPE
IN
IN
IN
POLARITY
Positive Edge
Negative Edge
Active High
DESCRIPTION
Positive line of the differential pair of system clock inputs.
Negative line of the differential pair of system clock inputs.
CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input
buffers and output drivers of the SDRAMs. Taking CKE LOW provides PRECHARGE
POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER
DOWN (row ACTIVE in any bank)
Enables the associated SDRAM command decoder when low and disables decoder when
high. When decoder is disabled, new commands are ignored and previous operations
continue. These input signals also disable all outputs (except CKE and ODT) of the
register(s) on the DIMM when both inputs are high. When both S[1:0] are high, all register
outputs (except CKE, ODT and Chip select) remain in the previous state. For modules
supporting 4 ranks, S[3:2] operate similarly to S[1:0] for a second set of register outputs.
On-Die Termination control signals
When sampled at the positive rising edge of the clock, CAS#, RAS#, and WE# define the
operation to be executed by the SDRAM.
Reference voltage for DQ0-DQ63 and CB0-CB7.
Reference voltage for A0-A15, BA0-BA2, RAS#, CAS#, WE#, S0#, S1#, CKE0, CKE1,
Par_In, ODT0 and ODT1.
Selects which SDRAM bank of eight is activated. BA0 - BA2 define to which bank an
Active, Read, Write or Precharge command is being applied. Bank address also
determines mode register is to be accessed during an MRS cycle.
Provided the row address for Active commands and the column address
and Auto Precharge bit for Read/Write commands to select one location out of the
memory array in the respective bank. A10 is sampled during a Precharge command to
determine whether the Precharge applies to one bank (A10 LOW) or all banks (A10
HIGH). If only one bank is to be precharged, the bank is selected by BA. A12 is also
utilized for BL 4/8 identification for ‘’BL on the fly’’ during CAS# command. The address
inputs also provide the op-code during Mode Register Set commands.
Data and Check Bit Input/Output pins
Power and ground for the DDR SDRAM input buffers and core logic.
Masks write data when high, issued concurrently with input data.
Power and ground for the DDR SDRAM input buffers and core logic.
Termination Voltage for Address/Command/Control/Clock nets.
Positive line of the differential data strobe for input and output data.
Negative line of the differential data strobe for input and output data.
TDQS, TDQS# is applicable for X8 DRAMs only. When enabled via Mode Register A11=1
in MR1, DRAM will enable the same termination resistance function on TDQS, TDQS#
that is applied to DQS, DQS#. When disabled via mode register A11=0 in MR1, DM,
TDQS will provide the data mask function and TDQS# is not used. X4/X16 DRAMs must
disable the TDQS function via mode register A11=0 in MR1
These signals are tied at the system planar to either VSS or VDDSPD to configure the
serial SPD EEPROM address range.
This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor
must be connected from the SDA bus line to V
DDSPD
on the system planar to act as a
pullup.
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be
connected from the SCL bus time to VDDSPD on the system planar to act as a pullup.
The RESET# pin is connected to the RESET# pin on each DRAM. When low, all DRAMs
are set to a known state.
S[3:0]#
IN
Active Low
ODT[1:0]
RAS#, CAS#,
WE#
VREFDQ
VREFCA
BA[2:0]
IN
IN
Supply
Supply
IN
Active High
Active Low
-
A[15:13,
12/BC,11,
10/AP,9:0]
DQ [63:0],
CB [7:0]
VDD, VSS
DM [8:0]
VDD, VSS
VTT
DQS[17:0]
DQS [17:0]#
TDQS[17:9],
TDQS[17:9]#
SA [2:0]
SDA
SCL
RESET#
IN
-
I/O
Supply
IN
Supply
Supply
I/O
I/O
OUT
-
-
Active High
Positive Edge
Negative Edge
IN
I/O
IN
IN
-
-
-
Viking Modular Solutions♦20091 Ellipse♦Foothill Ranch, CA 92610
Tel (800) 338-2361 Fax (949) 666-8159♦Website: http://www.vikingmodular.com
This Data Sheet is subject to change without notice.
Doc. # PS7JUxx7258xxx-LF Revision A1 Created By: Brian Ouellette
Page 3 of 19
DDR3
ECC MINI-UDIMM
PIN FUNCTION DESCRIPTION
SYMBOL
EVENT#
VDDSPD
TEST
TYPE
OUT
(open drain)
Supply
POLARITY
Active Low
-
DESCRIPTION
This signal indicates that a thermal event has been detected in the thermal sensing
device.The system should guarantee the electrical level requirement is met for the
EVENT pin on TS/SPD part.
Serial EEPROM positive power supply wired to a separate power pin at the connector
which supports from 3.0 Volt to 3.6 Volt (nominal 3.3V) operation.
Used by memory bus analysis tools (unused (NC) on memory DIMMs)
Viking Modular Solutions♦20091 Ellipse♦Foothill Ranch, CA 92610
Tel (800) 338-2361 Fax (949) 666-8159♦Website: http://www.vikingmodular.com
This Data Sheet is subject to change without notice.
Doc. # PS7JUxx7258xxx-LF Revision A1 Created By: Brian Ouellette
Page 4 of 19
DDR3
ECC MINI-UDIMM
MECHANICAL OUTLINE DUAL RANK MODULE
3.23
1.18
SIDE VIEW
DUAL RANK
FRONT
0.039
0.150
Max
Note: All dimensions in inches, tolerance: +/- 0.005"
BACK
0.04
+/- 0.004
Viking Modular Solutions♦20091 Ellipse♦Foothill Ranch, CA 92610
Tel (800) 338-2361 Fax (949) 666-8159♦Website: http://www.vikingmodular.com
This Data Sheet is subject to change without notice.
Doc. # PS7JUxx7258xxx-LF Revision A1 Created By: Brian Ouellette
Page 5 of 19
DIY/Open Source Hardware
京公网安备 11010802033920号
EEWORLD
