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DS1230Y/AB
256k Nonvolatile SRAM
www.maxim-ic.com
FEATURES
§
§
§
§
§
§
§
§
§
§
§
§
10 years minimum data retention in the
absence of external power
Data is automatically protected during power
loss
Replaces 32k x 8 volatile static RAM,
EEPROM or Flash memory
Unlimited write cycles
Low-power CMOS
Read and write access times as fast as 70 ns
Lithium energy source is electrically
disconnected to retain freshness until power is
applied for the first time
Full
±10%
V
CC
operating range (DS1230Y)
Optional
±5%
V
CC
operating range
(DS1230AB)
Optional industrial temperature range of
-40°C to +85°C, designated IND
JEDEC standard 28-pin DIP package
PowerCap Module (PCM) package
- Directly surface-mountable module
- Replaceable snap-on PowerCap provides
lithium backup battery
- Standardized pinout for all nonvolatile
SRAM products
- Detachment feature on PowerCap allows
easy removal using a regular screwdriver
PIN ASSIGNMENT
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
WE
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
28-Pin ENCAPSULATED PACKAGE
740-mil EXTENDED
NC
NC
NC
NC
V
CC
WE
OE
CE
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
NC
NC
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
GND V
BAT
34-Pin POWERCAP MODULE (PCM)
(USES DS9034PC POWERCAP)
PIN DESCRIPTION
A0 - A14
DQ0 - DQ7
CE
WE
OE
V
CC
GND
NC
- Address Inputs
- Data In/Data Out
- Chip Enable
- Write Enable
- Output Enable
- Power (+5V)
- Ground
- No Connect
1 of 13
083006
DS1230Y/AB
DESCRIPTION
The DS1230 256k Nonvolatile SRAMs are 262,144-bit, fully static, nonvolatile SRAMs organized as
32,768 words by 8 bits. Each NV SRAM has a self-contained lithium energy source and control circuitry
which constantly monitors V
CC
for an out-of-tolerance condition. When such a condition occurs, the
lithium energy source is automatically switched on and write protection is unconditionally enabled to
prevent data corruption. DIP-package DS1230 devices can be used in place of existing 32k x 8 static
RAMs directly conforming to the popular bytewide 28-pin DIP standard. The DIP devices also match the
pinout of 28256 EEPROMs, allowing direct substitution while enhancing performance. DS1230 devices
in the Low Profile Module package are specifically designed for surface-mount applications. There is no
limit on the number of write cycles that can be executed and no additional support circuitry is required for
microprocessor interfacing.
READ MODE
The DS1230 devices execute a read cycle whenever
WE
(Write Enable) is inactive (high) and
CE
(Chip
Enable) and
OE
(Output Enable) are active (low). The unique address specified by the 15 address inputs
(A
0
- A
14
) defines which of the 32,768 bytes of data is to be accessed. Valid data will be available to the
eight data output drivers within t
ACC
(Access Time) after the last address input signal is stable, providing
that
CE
and
OE
(Output Enable) access times are also satisfied. If
OE
and
CE
access times are not
satisfied, then data access must be measured from the later-occurring signal (
CE
or
OE
) and the limiting
parameter is either t
CO
for
CE
or t
OE
for
OE
rather than address access.
WRITE MODE
The DS1230 devices execute a write cycle whenever the
WE
and
CE
signals are active (low) after
address inputs are stable. The later-occurring falling edge of
CE
or
WE
will determine the start of the
write cycle. The write cycle is terminated by the earlier rising edge of
CE
or
WE
. All address inputs must
be kept valid throughout the write cycle.
WE
must return to the high state for a minimum recovery time
(t
WR
) before another cycle can be initiated. The
OE
control signal should be kept inactive (high) during
write cycles to avoid bus contention. However, if the output drivers are enabled (
CE
and
OE
active) then
WE
will disable the outputs in t
ODW
from its falling edge.
DATA RETENTION MODE
The DS1230AB provides full functional capability for V
CC
greater than 4.75 volts and write protects by
4.5 volts. The DS1230Y provides full functional capability for V
CC
greater than 4.5 volts and write
protects by 4.25 volts. Data is maintained in the absence of V
CC
without any additional support circuitry.
The nonvolatile static RAMs constantly monitor V
CC
. Should the supply voltage decay, the NV SRAMs
automatically write protect themselves, all inputs become “don’t care,” and all outputs become high-
impedance. As V
CC
falls below approximately 3.0 volts, a power switching circuit connects the lithium
energy source to RAM to retain data. During power-up, when V
CC
rises above approximately 3.0 volts
the power switching circuit connects external V
CC
to RAM and disconnects the lithium energy source.
Normal RAM operation can resume after V
CC
exceeds 4.75 volts for the DS1230AB and 4.5 volts for the
DS1230Y.
FRESHNESS SEAL
Each DS1230 device is shipped from Dallas Semiconductor with its lithium energy source disconnected,
guaranteeing full energy capacity. When V
CC
is first applied at a level greater than 4.25 volts, the lithium
energy source is enabled for battery back-up operation.
2 of 13
DS1230Y/AB
PACKAGES
The DS1230 devices are available in two packages: 28-pin DIP and 34-pin PowerCap Module (PCM).
The 28-pin DIP integrates a lithium battery, an SRAM memory and a nonvolatile control function into a
single package with a JEDEC-standard, 600-mil DIP pinout. The 34-pin PowerCap Module integrates
SRAM memory and nonvolatile control along with contacts for connection to the lithium battery in the
DS9034PC PowerCap. The PowerCap Module package design allows a DS1230 PCM device to be
surface mounted without subjecting its lithium backup battery to destructive high-temperature reflow
soldering. After a DS1230 PCM is reflow soldered, a DS9034PC PowerCap is snapped on top of the
PCM to form a complete Nonvolatile SRAM module. The DS9034PC is keyed to prevent improper
attachment. DS1230 PowerCap Modules and DS9034PC PowerCaps are ordered separately and shipped
in separate containers. See the DS9034PC data sheet for further information.
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground
Operating Temperature
Storage Temperature
Soldering Temperature
DIP Module
Caution: Do Not Reflow
PowerCap Module
*
-0.3V to +6.0V
0°C to 70°C, -40°C to +85°C for IND parts
-40°C to +70°C, -40°C to +85°C for IND parts
+260°C for 10 seconds
(Wave or Hand Solder Only)
See IPC/JEDEC J-STD-020
This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operation sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
PARAMETER
DS1230AB Power Supply Voltage
DS1230Y Power Supply Voltage
Logic 1
Logic 0
SYMBOL
V
CC
V
CC
V
IH
V
IL
MIN
4.75
4.5
2.2
0.0
TYP
5.0
5.0
MAX
5.25
5.5
V
CC
0.8
(t
A
: See Note 10)
UNITS
V
V
V
V
NOTES
DC ELECTRICAL
CHARACTERISTICS
PARAMETER
Input Leakage Current
I/O Leakage Current
CE
³
V
IH
£
V
CC
Output Current @ 2.4V
Output Current @ 0.4V
Standby Current
CE
=2.2V
Standby Current
CE
=V
CC
-0.5V
Operating Current
Write Protection Voltage (DS1230AB)
Write Protection Voltage (DS1230Y)
(V
CC
=5V
±
5% for DS1230AB)
(t
A
: See Note 10) (V
CC
=5V
±
10% for DS1230Y)
SYMBOL
I
IL
I
IO
I
OH
I
OL
I
CCS1
I
CCS2
I
CCO1
V
TP
V
TP
3 of 13
4.50
4.25
4.62
4.37
MIN
-1.0
-1.0
-1.0
2.0
200
50
600
150
85
4.75
4.5
TYP
MAX
+1.0
+1.0
UNITS
mA
mA
mA
mA
mA
mA
mA
V
V
NOTES
DS1230Y/AB
CAPACITANCE
PARAMETER
Input Capacitance
Input/Output Capacitance
SYMBOL
C
IN
C
I/O
MIN
TYP
5
5
MAX
10
10
pF
pF
(t
A
=25°C)
UNITS
NOTES
AC ELECTRICAL
CHARACTERISTICS
(V
CC
=5V
±
5% for DS1230AB)
(t
A
: See Note 10) (V
CC
=5V
±
10% for DS1230Y)
DS1230AB-100
DS1230Y-100
MIN
100
85
45
85
5
25
30
5
35
100
50
100
MAX
ns
ns
ns
ns
ns
ns
5
5
UNITS
NOTES
DS1230AB-70 DS1230AB-85
DS1230Y-85
PARAMETER SYMBOL DS1230Y-70
MIN MAX MIN MAX
Read Cycle
Time
Access Time
to Output
Valid
OE
CE
t
RC
t
ACC
t
OE
t
CO
t
COE
t
OD
70
70
35
70
5
85
to Output
Valid
or
CE
to
Output Active
OE
Output High Z
from
Deselection
Output Hold
from Address
Change
Write Cycle
Time
Write Pulse
Width
Address Setup
Time
Write Recovery
Time
Output High Z
from
WE
Output Active
from
WE
Data Setup
Time
Data Hold
Time
t
OH
5
5
5
ns
t
WC
t
WP
t
AW
t
WR1
t
WR2
t
ODW
t
OEW
t
DS
t
DH1
t
DH2
70
55
0
5
15
25
5
30
0
10
85
65
0
5
15
30
5
35
0
10
4 of 13
100
75
0
5
15
35
5
40
0
10
ns
ns
ns
ns
ns
ns
ns
ns
12
13
5
5
4
12
13
3
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