DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD784054(A)
16-BIT SINGLE-CHIP MICROCONTROLLER
DESCRIPTION
The
µ
PD784054(A) is a product of the 78K/IV series, and based on the
µ
PD784044(A) with the real-time output
function and two units of timers/counters deleted and a standby function invalid mode provided. A stricter quality
assurance program applies to the
µ
PD784054(A) compared to the
µ
PD784054 (standard model).
The
µ
PD784054(A) is provided with many peripheral hardware functions such as ROM, RAM, I/O port, 10-bit
resolution A/D converter, timer, serial interface, and interrupt functions, in addition to a high-speed, high-performance
CPU.
Moreover, a flash memory model,
µ
PD78F4046
Note
, that can operate on the same supply voltage as the mask ROM
model, and many development tools are under development.
Note
Use for functional evaluation only.
The functions are described in detail in the following User’s Manuals. Be sure to read these manuals when
designing your system.
µ
PD784054 User’s Manual - Hardware
: U11719E
78K/IV Series User’s Manual - Instruction : U10905E
FEATURES
• Higher reliability compared to the
µ
PD784054
• Minimum instruction execution time
• I/O port
• Timer
• A/D converter
• Watchdog timer
• Supply voltage
: 160 ns (with 12.5-MHz internal clock) ···
µ
PD784054(A)
200 ns (with 10-MHz internal clock) ···
µ
PD784054(A1), (A2)
: 64 lines
: 16-bit timer
×
3 units
: 10-bit resolution
×
16 channels
: 1 channel
: V
DD
= 4.5 to 5.5 V
• Serial interface UART/IOE (3-wire serial I/O) : 2 channels
• Standby function HALT/STOP/IDLE/standby function invalid mode
APPLICATION FIELDS
Automotive appliances, etc.
In this document, in addition to the
µ
PD784054(A), the
µ
PD784054(A1) and 784054(A2) are also explained.
However, unless otherwise specified, the
µ
PD784054(A) is treated as the representative model throughout
this document.
The information in this document is subject to change without notice.
Document No. U13122EJ1V0DS00 (1st edition)
Date Published January 1998 N CP(K)
Printed in Japan
©
1998
µ
PD784054(A)
ORDERING INFORMATION
Part Number
Package
80-pin plastic QFP (14
×
14 mm)
80-pin plastic QFP (14
×
14 mm)
80-pin plastic QFP (14
×
14 mm)
Internal ROM (bytes) Internal RAM (bytes)
32 K
32 K
32 K
1024
1024
1024
µ
PD784054GC(A)-×××-3B9
µ
PD784054GC(A1)-×××-3B9
µ
PD784054GC(A2)-×××-3B9
Remark
×××
indicates ROM code suffix.
QUALITY GRADE
Special
Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by
NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
Differences between
µ
PD784054 and
µ
PD784054(A)
Part Number
Item
Quality grade
Operating ambient temperature (T
A
)
Operating frequency
Minimum instruction execution time
DC characteristics
AC characteristics
A/D converter characteristics
Standard
–10 to + 70˚C
8 to 32 MHz
125 ns (with 16-MHz internal clock)
V
DD
supply current differs.
Bus timing and serial operation differ.
Conversion time and sampling time differ.
µ
PD784054
Special
µ
PD784054(A)
–40 to +85 ˚C
8 to 25 MHz
160 ns (with 12.5-MHz internal clock)
Differences between
µ
PD784054(A), 784054(A1) and 784054(A2)
Part Number
Item
Operating ambient temperature (T
A
)
Operating frequency
Minimum instruction execution time
DC characteristics
AC characteristics
A/D converter characteristics
µ
PD784054(A)
–40 to +85 ˚C
8 to 25 MHz
160 ns (with 12.5-MHz
internal clock)
retention current differ.
µ
PD784054(A1)
–40 to +110 ˚C
8 to 20 MHz
200 ns
(with 10-MHz internal clock)
µ
PD784054(A2)
–40 to +125 ˚C
Analog pin input leakage current, V
DD
supply current and data
Bus timing and serial operation differ.
AV
REF
current and A/D converter data retention current differ.
2
µ
PD784054(A)
Product Development of 78K/IV Series
: Under mass production
: Under development
Standard models
For I
2
C bus
For multimaster I
2
C bus
µ
PD784038Y
µ
PD784038
Improved internal memory capacity,
pin compatible with
µ
PD784026
For multimaster I
2
C bus
µ
PD784225Y
µ
PD784225
80 pins, ROM correction added
For multimaster I
2
C bus
µ
PD784026
A/D, 16-bit timer, improved
power management
µ
PD784216Y
µ
PD784216
100 pins, I/O, improved
internal memory capacity
µ
PD784218Y
µ
PD784218
Improved internal memory
capacity, ROM correction added
µ
PD784054
µ
PD784046
Internal 10-bit A/D
ASSP models
µ
PD784955
For DC converter control
µ
PD784908
Internal IEBus
TM
controller
For multimaster I
2
C bus
µ
PD78F4943
For CD-ROM
Flash memory 56 KB
µ
PD784928Y
µ
PD784928
Improved functions of
µ
PD784915
µ
PD784915
Software servo control,
internal analog circuit
for VCR, improved timer
3
µ
PD784054(A)
FUNCTION LIST
Item
Number of basic
instructions (mnemonics)
General-purpose register
Minimum instruction
execution time
Internal
memory
Memory space
I/O port
Total
Input
I/O
ROM
RAM
113
8 bits
×
16 registers
×
8 banks, or 16 bits
×
8 registers
×
8 banks (memory mapping)
• 160 ns (with internal 12.5-MHz clock):
µ
PD784054(A)
• 200 ns (with internal 10-MHz clock) :
µ
PD784054(A1), (A2)
32K bytes
1024 bytes
1M bytes with program/data combined
64 pins
17 pins
47 pins
Function
Pins with
Pins with 29 pins
ancillary
pull-up
Note
resistors
functions
Timer
Timer 0
(16 bits)
Timer 1
(16 bits)
Timer 4
(16 bits)
A/D converter
Serial interface
Watchdog timer
Interrupt
: Timer register
×
1,
capture/compare register
×
4
: Timer register
×
1,
compare register
×
2
: Timer register
×
1,
compare register
×
2
Pulse output possible
• Toggle output
• Set/reset output
Pulse output possible
• Toggle output
• Set/reset output
10-bit resolution
×
16 channels
UART/IOE (3-wire serial I/O): 2 channels (with baud rate generator)
1 channel
Hardware source 23 (internal: 19, external: 8 (internal/external: 4))
Software source
Non-maskable
Maskable
BRK instruction, BRKCS instruction, operand error
Internal: 1, external: 1
Internal: 18, external: 7 (internal/external: 4)
• 4 levels of programmable priorities
• 3 processing formats: vectored interrupt/macro service/context switching
Bus sizing
Standby
Supply voltage
Package
8-bit/16-bit external data bus width selectable
HALT/STOP/IDLE/standby function invalid mode
V
DD
= 4.5 to 5.5 V
80-pin plastic QFP (14
×
14 mm)
Note
The pins with ancillary functions are included in the I/O pins.
4
µ
PD784054(A)
CONTENTS
1. DIFFERENCES BETWEEN
µ
PD784054(A) AND
µ
PD784044(A), 784046(A) ................................. 7
2. PIN CONFIGURATION (Top View) ..................................................................................................... 8
3. SYSTEM CONFIGURATION EXAMPLE ...........................................................................................10
4. BLOCK DIAGRAM ............................................................................................................................. 11
5. PIN FUNCTIONS ................................................................................................................................12
5.1
5.2
5.3
Port Pins .................................................................................................................................................... 12
Pins Other Than Port Pins ...................................................................................................................... 14
I/O Circuits of Pins and Processing of Unused Pins .......................................................................... 16
6. CPU ARCHITECTURE .......................................................................................................................18
6.1
6.2
Memory Space .......................................................................................................................................... 18
CPU Registers ........................................................................................................................................... 20
6.2.1
6.2.2
6.2.3
General-purpose registers ............................................................................................................. 20
Control registers ............................................................................................................................. 21
Special function registers (SFRs) .................................................................................................. 22
7. PERIPHERAL HARDWARE FUNCTIONS ........................................................................................27
7.1
7.2
7.3
7.4
7.5
7.6
7.7
Ports ........................................................................................................................................................... 27
Clock Generation Circuit ......................................................................................................................... 28
Timer .......................................................................................................................................................... 30
A/D Converter ........................................................................................................................................... 32
Serial Interface .......................................................................................................................................... 33
7.5.1
Asynchronous serial interface/3-wire serial I/O (UART/IOE) ....................................................... 34
Edge Detection Circuit ............................................................................................................................ 36
Watchdog Timer ........................................................................................................................................ 36
8. INTERRUPT FUNCTION....................................................................................................................37
8.1
8.2
8.3
8.4
Interrupt Source ....................................................................................................................................... 37
Vectored Interrupt .................................................................................................................................... 39
Context Switching .................................................................................................................................... 40
Macro Service ........................................................................................................................................... 41
9. LOCAL BUS INTERFACE .................................................................................................................44
9.1
9.2
9.3
9.4
Memory Expansion .................................................................................................................................. 45
Memory Space .......................................................................................................................................... 46
Programmable Wait .................................................................................................................................. 46
Bus Sizing Function ................................................................................................................................. 46
5
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