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PACE1754-20CMB

Description
Microprocessor Circuit, CMOS, CDIP64
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size143KB,16 Pages
ManufacturerPyramid Semiconductor Corporation
Websitehttp://www.pyramidsemiconductor.com/
Download Datasheet Parametric View All

PACE1754-20CMB Overview

Microprocessor Circuit, CMOS, CDIP64

PACE1754-20CMB Parametric

Parameter NameAttribute value
MakerPyramid Semiconductor Corporation
Parts packaging codeDIP
package instructionDIP-64
Contacts64
Reach Compliance Codecompliant
JESD-30 codeR-CDIP-T64
length42.2402 mm
Number of terminals64
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeDIP
Package shapeRECTANGULAR
Package formIN-LINE
Certification statusNot Qualified
Maximum slew rate40 mA
Maximum supply voltage5.5 V
Minimum supply voltage4.5 V
Nominal supply voltage5 V
surface mountNO
technologyCMOS
Temperature levelMILITARY
Terminal formTHROUGH-HOLE
Terminal pitch1.27 mm
Terminal locationDUAL
width15.24 mm
uPs/uCs/peripheral integrated circuit typeMICROPROCESSOR CIRCUIT
PACE1754/SOS
PROCESSOR INTERFACE CIRCUIT (PIC)
CMOS/SOS SPACE PROCESSOR
MICROPERIPHERAL
FEATURES
The PACE1754 (PIC) is a support chip for the
PACE1750A/AE Processors. It eliminates the
SSI/MSI Logic and external system functions
required in typical 1750A implementations.
Provides a significant savings in part-count and
power dissipation enhancing reliability and
overall system speed performance.
Provides an optimal interface when used with
the PACE1753 MMU/COMBO in a full 1750A
implementation.
Provides the following additional important
system functions:
— Programmable READY for memory and I/O
— Automatic READY during self-test and
internal I/O instructions
— 100KHz timer clock output provided
— Programmable system watchdog—ranges
from 1 µs to 1 minute
— Programmable Bus time-out function
— Memory Parity generation/detection
— Error detection of unimplemented memory
and/or I/O space addressing
— First failing memory address register for
diagnostics
— High drive three-state address latches
— Built-in system test program—automatically
tests the PACE1750A/AE CPUs, PACE1753
MMU/COMBO, PACE1754 PIC and system
address lines as well as memory and I/O
strobes
— System configuration decoding and buffering
— Interrupt acknowledge decoder and strobe
— Start up ROM support per MIL-STD-1750A
— Memory or I/O READ/WRITE three-state
strobes with external three-state control for
DMA applications
Available with Class S manufacturing,
screening, and testing.
SOS insulated substrate technology provides
absolute latch-up immunity and excellent SEU
tolerance.
SOS devices are fully interchangeable with
application-proven SMD CMOS P1754 devices.
20, 25 and 30 MHz operation over full Military
Temperature Range
Single 5V ± 10% Power Supply
Available in:
— 68-Lead Quad Pack with optional Gull Wing
Surface Mount
PACE1754 PROCESSOR INTERFACE
CIRCUIT DESCRIPTION
The PACE1754 Processor Interface Circuit (PIC) is a single
chip implementation of many special system functions that
are often required when using the PACE1750A/AE, a single
chip microprocessor. The PIC allows a system designer to
design a higher performance, more effecient microprocessor
system which uses less power and takes up less board
space.
The PIC provides many important system functions. These
functions are governed by respective bit positions in a
programmable Control Register which is incorporated in the
PIC. The individual bits of the control register are set to
select the various features and are set to a specified default
value upon Reset.
Document #
MICRO-9
REV B
Revised August 2005
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