P1750A/SOS
SINGLE CHIP, 20MHz to 30MHz,
CMOS/SOS SPACE PROCESSOR
FEATURES
Implements the MIL-STD-1750A Instruction Set
Architecture
CMOS/SOS Processor with 32 and 48-Bit
Floating Point Arithmetic
Integer DAIS Mix Performance
3.0 MIPS at 30 MHz
Available with Class S type manufacturing,
screening, and testing
SOS Insulated substrate technology provides
absolute latch up immunity and excellent SEU
tolerance
Total Dose
≥
100 Krads (Si)
20, 25, and 30 MHz operation over the Military
Temperature Range
Extensive Error and Fault Management and
Interrupt Capability
Built-In Self Test
24 User Accessible Registers
Single 5V ± 10% Power Supply
TTL Signal Level compatible Inputs and
Outputs
Multiprocessor and Co-processor capability
Built-In Function (BIF) for User Defined
Instructions
Two programmable Timers
SOS devices are fully interchangeable with
application-proven CMOS P1750A Processors;
SMD 5962-87665
Available in:
- 68-Lead Quad Pack (Leaded Chip Carrier) with
Optional Gull Wing
GENERAL DESCRIPTION
The PACE1750A is a general purpose, application-proven,
single chip, 16-bit CMOS microprocessor designed for
high performance floating point and integer arithmetic,
with extensive real time environment support. It offers a
variety of data types, including bits, bytes, 16-bit and 32-
bit integers, and 32-bit and 48-bit floating point numbers.
It provides 13 addressing modes, including direct, indirect,
indexed, based, based indexed and immediate long and
short, and it can access 2 MWords of segmented memory
space (64 KWords segments without use of a MIL-STD-
1750A MMU).
The PACE1750A offers a well-rounded instruction set
with 130 instruction types, including a comprehensive
integer, floating point, integer-to-floating point and floating
point-to-integer set, a variety of stack manipulation
instructions, high level language support instructions
such as Compare Between Bounds and Loop Control
Instructions. It also offers some unique instructions such
as vectored l/O, supports executive and user modes, and
provides an escape mechanism which allows user-defined
instructions using a coprocessor. The instruction set is
fully compliant with MIL-STD-1750A.
The chip includes 16 general purpose registers, 8 other
user-accessible registers, and an array of real time
application support resources, such as 2 programmable
timers, a complete interrupt controller supporting 16
levels of prioritized internal and external interrupts, and a
faults and exceptions handler controlling internally and
externally generated faults.
The P1750A uses a single multiplexed 16-bit parallel bus.
Status signals are provided to determine whether the
processor is in the memory or I/O bus cycle, reading and
writing, and whether the bus cycle is for data or instructions.
The basic bus cycle is 4 clocks long. The P1750A will
extend the cycle by insertion of wait states in the address
and data phases (in response to RDYA and RDYD
signals, repectively) and will hold the machine in HI-Z if
this CPU has not acquired the bus. A typical non-bus
cycle is three clocks long. However, variable length
cycles are used for such repetitive operations as multiply,
divide, scale and normalize, reducing significantly the
number of CPU CLOCKS per operation step and resulting
in very fast integer and floating point execution times.
Document #
MICRO-6
REV B
Revised August 2005
P1750A/SOS
ABSOLUTE MAXIMUM RATINGS
1
Supply Voltage Range
Input Voltage Range
-0.5V to 7.0V
-0.5V to V
CC
+ 0.5V
RECOMMENDED OPERATING
CONDITIONS
Supply Voltage Range
4.5V to 5.5V
Case Operating Temperature -55°C to +125°C
Range
Storage Temperature Range -65°C to + 150°C
Input Current Range
Voltage Applied to Inputs
Current Applied to Outputs
3
-30mA to +5mA
-0.5V to VCC + 0.5V
150 mA
Maximum Power Dissipation
2
1.5W
Operating worst case power
dissipation (outputs open):
0.5W at 20MHz
0.6W at 25MHz
0.7W at 30MHz
Lead Temperature Range
(soldering 10 seconds)
Thermal resistance,
junction-to-case (θ
JC
):
Packages QL and QG
300°C
8°C/W
NOTES:
1. Stresses above the absolute maximum rating may cause permanent
damage to the device. Extended operation at the maximum levels may
degrade performance and affect reliability.
2. Must withstand the added power dissipation due to short circuit test
e.g., I
OS
3. Duration one second or less.
RADIATION HARDNESS
Total Dose - (All specification still within limits) > 1 x 10
5
Rad (Si) [1]
Neutron Hardness
Single Event Upset
Radiation Induced Latch Up
NOTES:
[1] Tested MIL-STD-883 TM 1019
[2] CMOS/SOS is a majority carrier technology and is therefore
unaffected. CMOS/SOS typically withstands neutron radiation to
> 10
15
(limit of available test equipment). Testing waived, MIL-
STD-883 TM 5005
[3] Tested at Brookhaven National Laboratory
[4] Physically impossible for SOS device to suffer destructive latch
up from natural space ionizing radiation.
1 x 10
15
neutrons/cm
2
[2]
> 9 x 10
-10
errors per day [3]
Absolute immunity [4]
Document #
MICRO-6
REV B
Page 2 of 20
P1750A/SOS
SIGNAL PROPAGATION DELAYS
1,2
(continued)
20 MHz
25 MHz
Min
Max
30 MHz
Min
Max
Unit
Symbol
Parameter
IB
0
-IB
15
SNEW
TRIGO RST
Min
Max
t
FC(IBD)V
t
C(SNW)
t
FC(TGO)
t
C(DME)
t
FC(NPU)
t
C(ER)
t
RSTL(NPU)
t
REQV(C)
t
C(REQ)X
t
FV(BB)H
t
BBH(F)X
t
IRV(C)
t
C(IR)X
34
34
34
44
44
44
60
50
0
10
5
5
0
15
25
24
5
5
5
0
10
5
5
0
15
25
34
30
30
40
40
40
55
45
0
10
5
5
0
15
20
20
5
5
32
28
28
38
38
38
52
40
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
RSTL(DMA ENL)
DMA enable
DMA enable
Normal power up
Clock to major error unrecoverable
RESET
Console request
Console request
Level sensitive faults
Level sensitive faults
IOL
1-2
INT user interrupt (0-5) setup
Power down interrupt level sensitive
hold
t
RSTL
(t
RSTH
)
Reset pulse width
t
C(XX)Z
t
f(F)
, t
1(1)
t
r
, t
f
Clock to three-state
Edge sensitiive pulse width
Clock rise and fall
18
5
ns
ns
ns
Notes
1. 4.5V
≤
V
CC
≤
5.5V, –55°C
≤
T
C
≤
+125°C. Unless otherwise specified, testing shall be conducted at worst-case conditions.
2. All timing parameters are composed of Three elements. The first "t" stands for timing. The second represents the "from" signal. The third in
parentheses indicates "to" signal. When the CPU clock is one of the signal elements, either the rising edge "C" or the falling edge "FC" is referenced.
When other elements are used, an additional suffix indicates the final logic level of the signal. "L" - low level, "H" - high level, "V" - valid, "Z" - high
impedance, "X" - don't care, "LH" - low to high, "ZH" - high impedance to high, "R" - read cycle, and "W" - write cycle.
3. Functional test shall consist of the same functional test used when testing the equivalent bulk CMOS, MIL-STD-883 Compliant, Class B SMD 5962-
87665 device.
Document #
MICRO-6
REV B
Page 5 of 20
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