PI7C9X20303SLFDE datasheet, PDF

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PI7C9X20303SLFDE: DescriptionPCI Bus Controller, CMOS, PQFP128, 14 X 14 MM, GREEN, MO-026, LQFP-128; CategoryThe embedded processor and controller Microcontrollers and processors; File Size513KB，76 Pages; ManufacturerDiodes Incorporated; Environmental Compliance

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PI7C9X20303SLFDE Overview

PCI Bus Controller, CMOS, PQFP128, 14 X 14 MM, GREEN, MO-026, LQFP-128

PI7C9X20303SLFDE Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Diodes Incorporated
package instruction	14 X 14 MM, GREEN, MO-026, LQFP-128
Reach Compliance Code	compliant
ECCN code	EAR99
Address bus width
Bus compatibility	PCI
maximum clock frequency	100 MHz
Drive interface standards	IEEE 1149.6; IEEE 1149.1
External data bus width
JESD-30 code	S-PQFP-G128
length	14 mm
Humidity sensitivity level	1
Number of terminals	128
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	LFQFP
Package shape	SQUARE
Package form	FLATPACK
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum supply voltage	1.1 V
Minimum supply voltage	0.9 V
Nominal supply voltage	1 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	GULL WING
Terminal pitch	0.4 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	14 mm
uPs/uCs/peripheral integrated circuit type	BUS CONTROLLER, PCI

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PI7C9X20303SL

PCI EXPRESS® PACKET SWITCH

DATASHEET

REVISION 1.1

July 2009

3545 North 1

Street, San Jose, CA 95134

Telephone: 1-877-PERICOM, (1-877-737-4266)

FAX: 408-435-1100

Internet:

http://www.pericom.com

PI7C9X20303SL

3Port-3Lane PCI Express® Switch

SlimLine

Family

Datasheet

DISCLAIMER

The information contained in this document is proprietary and confidential to Pericom Semiconductor Cooperation (PSC). No part of this

document may be copied or reproduced in any form or by any means without prior written consent of PSC.

The information in this document is subjected to change without notice.

PSC retains the right to make changes to this document at any time

without notice. While the information contained in this document has been checked for accuracy, such information is preliminary, and PSC does

not warrant the accuracy and completeness of such information. PSC does not assume any liability or responsibility for damages arising from any

use of the information contained in this document.

LIFE SUPPORT POLICY

Pericom Semiconductor Corporation’s products are not authorized for use as critical components in life support devices or systems unless a

specific written agreement pertaining to such intended use is executed between the manufacturer and an officer of PSC.

Life support devices or system are devices or systems which:

a) Are intended for surgical implant into the body or

b) Support or sustain life and whose failure to perform, when properly used in accordance with instructions for use provided in the

labeling, can be reasonably expected to result in a significant injury to the user.

A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the

failure of the life support device or system, or to affect its safety or effectiveness. Pericom Semiconductor Corporation reserves the right to

make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best

possible product. Pericom Semiconductor does not assume any responsibility for use of any circuitry described other than the circuitry

embodied in a Pericom Semiconductor product. The Company makes no representations that circuitry described herein is free from patent

infringement or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any

patent, patent rights or other rights, of Pericom Semiconductor Corporation.

All other trademarks are of their respective companies.

Page 2 of 76

July 2009 – Revision 1.1

Pericom Semiconductor

PI7C9X20303SL

3Port-3Lane PCI Express® Switch

SlimLine

Family

Datasheet

TABLE OF CONTENTS

FEATURES.........................................................................................................................................................10

GENERAL DESCRIPTION..............................................................................................................................11

PIN DESCRIPTION...........................................................................................................................................12

3.1

3.2

3.3

3.4

3.5

4.1

PCI EXPRESS INTERFACE SIGNALS ....................................................................................................12

PORT CONFIGURATION SIGNALS .......................................................................................................12

MISCELLANEOUS SIGNALS..................................................................................................................12

JTAG BOUNDARY SCAN SIGNALS ......................................................................................................13

POWER PINS.............................................................................................................................................14

PIN LIST

128-PIN LQFP.......................................................................................................................15

PIN ASSIGNMENTS .........................................................................................................................................15

FUNCTIONAL DESCRIPTION.......................................................................................................................16

5.1

PHYSICAL LAYER CIRCUIT ..................................................................................................................16

5.2

DATA LINK LAYER (DLL)......................................................................................................................18

5.3

TRANSACTION LAYER RECEIVE BLOCK (TLP DECAPSULATION) ..............................................18

5.4

ROUTING ..................................................................................................................................................18

5.5

TC/VC MAPPING......................................................................................................................................19

5.6

QUEUE.......................................................................................................................................................19

5.6.1

PH .......................................................................................................................................................19

5.6.2

PD .......................................................................................................................................................19

5.6.3

NPHD .................................................................................................................................................19

5.6.4

CPLH ..................................................................................................................................................19

5.6.5

CPLD ..................................................................................................................................................19

5.7

TRANSACTION ORDERING...................................................................................................................20

5.8

PORT ARBITRATION ..............................................................................................................................20

5.9

FLOW CONTROL .....................................................................................................................................21

5.10 TRANSATION LAYER TRANSMIT BLOCK (TLP ENCAPSULATION) .............................................21

EEPROM INTERFACE AND SYSTEM MANAGEMENT BUS..................................................................22

6.1

EEPROM INTERFACE .............................................................................................................................22

6.1.1

AUTO MODE EERPOM ACCESS .....................................................................................................22

6.1.2

EEPROM MODE AT RESET..............................................................................................................22

6.1.3

EEPROM SPACE ADDRESS MAP ....................................................................................................22

6.1.4

MAPPING EEPROM CONTENTS TO CONFIGURATION REGISTERS..........................................24

6.2

SMB

INTERFACE .................................................................................................................................29

REGISTER DESCRIPTION.............................................................................................................................30

7.1

REGISTER TYPES ....................................................................................................................................30

7.2

TRANSPARENT MODE CONFIGURATION REGISTERS ....................................................................30

7.2.1

VENDOR ID REGISTER – OFFSET 00h ...........................................................................................32

7.2.2

DEVICE ID REGISTER – OFFSET 00h.............................................................................................32

7.2.3

COMMAND REGISTER – OFFSET 04h............................................................................................32

7.2.4

PRIMARY STATUS REGISTER – OFFSET 04h.................................................................................33

7.2.5

REVISION ID REGISTER – OFFSET 08h .........................................................................................33

7.2.6

CLASS CODE REGISTER – OFFSET 08h .........................................................................................33

7.2.7

CACHE LINE REGISTER – OFFSET 0Ch.........................................................................................34

Page 5 of 76

July 2009 – Revision 1.1

Pericom Semiconductor

PI7C9X20303SLFDE Related Products

	PI7C9X20303SLFDE	PI7C9X20303SLFDEX	PI7C9X20303SLFDX	PI7C9X20303SLFD
Description	PCI Bus Controller, CMOS, PQFP128, 14 X 14 MM, GREEN, MO-026, LQFP-128	PCI Bus Controller, CMOS, PQFP128, LQFP-128	PCI Bus Controller, CMOS, PQFP128, 14 X 14 MM, GREEN, MO-026, LQFP-128	PCI Bus Controller, CMOS, PQFP128, 14 X 14 MM, GREEN, MO-026, LQFP-128
package instruction	14 X 14 MM, GREEN, MO-026, LQFP-128	LFQFP,	LFQFP,	14 X 14 MM, GREEN, MO-026, LQFP-128
Reach Compliance Code	compliant	compliant	unknown	unknown
ECCN code	EAR99	EAR99	EAR99	EAR99
Bus compatibility	PCI	PCI	PCI	PCI
maximum clock frequency	100 MHz	100 MHz	100 MHz	100 MHz
Drive interface standards	IEEE 1149.6; IEEE 1149.1	IEEE 1149.6; IEEE 1149.1	IEEE 1149.6; IEEE 1149.1	IEEE 1149.6; IEEE 1149.1
JESD-30 code	S-PQFP-G128	S-PQFP-G128	S-PQFP-G128	S-PQFP-G128
length	14 mm	14 mm	14 mm	14 mm
Number of terminals	128	128	128	128
Maximum operating temperature	85 °C	85 °C	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C	-40 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	LFQFP	LFQFP	LFQFP	LFQFP
Package shape	SQUARE	SQUARE	SQUARE	SQUARE
Package form	FLATPACK	FLATPACK	FLATPACK	FLATPACK
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.6 mm	1.6 mm	1.6 mm	1.6 mm
Maximum supply voltage	1.1 V	1.1 V	1.1 V	1.1 V
Minimum supply voltage	0.9 V	0.9 V	0.9 V	0.9 V
Nominal supply voltage	1 V	1 V	1 V	1 V
surface mount	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING
Terminal pitch	0.4 mm	0.4 mm	0.4 mm	0.4 mm
Terminal location	QUAD	QUAD	QUAD	QUAD
width	14 mm	14 mm	14 mm	14 mm
uPs/uCs/peripheral integrated circuit type	BUS CONTROLLER, PCI	BUS CONTROLLER, PCI	BUS CONTROLLER, PCI	BUS CONTROLLER, PCI
Maker	Diodes Incorporated	-	Diodes Incorporated	Diodes Incorporated

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