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VIC068A-GMB

Description
VME Bus Controller, MOS, CPGA145, CAVITY-UP, CERAMIC, PGA-145
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size828KB,15 Pages
ManufacturerCypress Semiconductor
Download Datasheet Parametric Compare View All

VIC068A-GMB Overview

VME Bus Controller, MOS, CPGA145, CAVITY-UP, CERAMIC, PGA-145

VIC068A-GMB Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerCypress Semiconductor
Parts packaging codePGA
package instructionPGA, PGA145,15X15
Contacts145
Reach Compliance Codenot_compliant
ECCN code3A001.A.2.C
Address bus width7
Bus compatibility68XXX FAMILY
Drive interface standardsIEEE 1014
External data bus width8
JESD-30 codeS-CPGA-P145
JESD-609 codee0
length40.0685 mm
Number of terminals145
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codePGA
Encapsulate equivalent codePGA145,15X15
Package shapeSQUARE
Package formGRID ARRAY
power supply5 V
Certification statusNot Qualified
Filter level38535Q/M;38534H;883B
Maximum seat height5.207 mm
Maximum slew rate150 mA
Maximum supply voltage5.5 V
Minimum supply voltage4.5 V
Nominal supply voltage5 V
surface mountNO
technologyMOS
Temperature levelMILITARY
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formPIN/PEG
Terminal pitch2.54 mm
Terminal locationPERPENDICULAR
width40.0685 mm
uPs/uCs/peripheral integrated circuit typeBUS CONTROLLER, VME
VIC068A
VMEbus Interface Controller
Features
• Complete VMEbus interface controller and arbiter
— 58 internal registers provide configuration control
and status of VMEbus and local operations
— Drives arbitration, interrupt, address modifier utility,
strobe, address lines A07 through A01 and data lines
D07 through D00 directly, and provides signals for
control logic to drive remaining address and data
lines
— Direct connection to 68xxx family and mappable to
non-68xxx processors
Complete master/slave capability
— Supports read, write, write posting, and block trans-
fers
— Accommodates VMEbus timing requirements with
internal digital delay line (
1
2
-clock granularity)
— Programmable metastability delay
— Programmable data acquisition delays
— Provides timeout timers for local bus and VMEbus
transactions
Interleaved block transfers over VMEbus
— Acts as DMA master on local bus
— Programmable burst count, transfer length, and in-
terleaved period interval
— Supports local module-based DMA
Arbitration support
— Supports single-level, priority and round robin arbi-
tration
— Supports fair request option as requester
Interrupt support
— Complete support for the VMEbus interrupts: inter-
rupter and interrupt handler
— Seven local interrupt lines
— 8-level interrupt priority encode
— Total of 29 interrupts mapped through the VIC068A
Miscellaneous features
— Refresh option for local DRAM
— Four broadcast location monitors
— Four module-specific location monitors
— Eight interprocessor communications registers
— PGA or QFP packages
— Compatible with IEEE Specification 1014, Rev. C
— Supports RMC operations
See the
VMEbus Interface Handbook
for more informa-
tion
Functional Description
The VMEbus interface controller (VIC068A) is a single chip
designed to minimize the cost and board area requirements
and to maximize performance of the VMEbus interface of a
VMEbus master/slave module. This can be implemented on
VIC068A either an 8-bit, 16-bit, or 32-bit VMEbus system. The
VIC068A performs all VMEbus system controller functions
plus many others, which simplify the development of
VIC068Aa VMEbus interface. The VIC068A utilizes patented
on-chip output buffers. These CMOS high-drive buffers pro-
vide direct connection to the address and data lines. In addi-
tion to these signals, the VIC068A connects directly to the ar-
bitration, interrupt, address modifier, utility and strobe lines.
Signals are provided which control data direction and latch
functions needed for a 32-bit implementation.
The VIC068A was developed through the efforts of a consor-
tium of board vendors, under the auspices of the VMEbus In-
ternational Trade Association (VITA). The VIC068A thus in-
sures compatibility between boards designed by different
manufacturers.
Cypress Semiconductor Corporation
Document #: 38-09004 Rev. **
3901 North First Street
San Jose
CA 95134 • 408-943-2600
Revised July 23, 1997

VIC068A-GMB Related Products

VIC068A-GMB VIC068A-GI
Description VME Bus Controller, MOS, CPGA145, CAVITY-UP, CERAMIC, PGA-145 VME Bus Controller, MOS, CPGA145, CAVITY-UP, CERAMIC, PGA-145
Is it Rohs certified? incompatible incompatible
Maker Cypress Semiconductor Cypress Semiconductor
Parts packaging code PGA PGA
package instruction PGA, PGA145,15X15 PGA, PGA145,15X15
Contacts 145 145
Reach Compliance Code not_compliant not_compliant
Address bus width 7 7
Bus compatibility 68XXX FAMILY 68XXX FAMILY
Drive interface standards IEEE 1014 IEEE 1014
External data bus width 8 8
JESD-30 code S-CPGA-P145 S-CPGA-P145
JESD-609 code e0 e0
length 40.0685 mm 40.0685 mm
Number of terminals 145 145
Maximum operating temperature 125 °C 85 °C
Minimum operating temperature -55 °C -40 °C
Package body material CERAMIC, METAL-SEALED COFIRED CERAMIC, METAL-SEALED COFIRED
encapsulated code PGA PGA
Encapsulate equivalent code PGA145,15X15 PGA145,15X15
Package shape SQUARE SQUARE
Package form GRID ARRAY GRID ARRAY
power supply 5 V 5 V
Certification status Not Qualified Not Qualified
Maximum seat height 5.207 mm 5.207 mm
Maximum slew rate 150 mA 150 mA
Maximum supply voltage 5.5 V 5.5 V
Minimum supply voltage 4.5 V 4.5 V
Nominal supply voltage 5 V 5 V
surface mount NO NO
technology MOS MOS
Temperature level MILITARY INDUSTRIAL
Terminal surface Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb)
Terminal form PIN/PEG PIN/PEG
Terminal pitch 2.54 mm 2.54 mm
Terminal location PERPENDICULAR PERPENDICULAR
width 40.0685 mm 40.0685 mm
uPs/uCs/peripheral integrated circuit type BUS CONTROLLER, VME BUS CONTROLLER, VME
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