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FAN7930B — Critical Conduction Mode PFC Controller
October 2010
FAN7930B
Critical Conduction Mode PFC Controller
Features
Additional OVP Detection Pin
Input Voltage Absent Detection Circuit
Maximum Switching Frequency Limitation
Internal Soft-Start and Overshoot-less Control
Internal Total Harmonic Distortion (THD) Optimizer
Precise Adjustable Output Over-Voltage Protection
Open-Feedback Protection and Disable Function
Zero Current Detector
150μs Internal Startup Timer
MOSFET Over-Current Protection
Under-Voltage Lockout with 3.5V Hysteresis
Low Startup and Operating Current
Totem-Pole Output with High State Clamp
+500/-800mA
Peak Gate Drive Current
8-Pin Small Outline Package (SOP)
Description
The FAN7930B is an active power factor correction
(PFC) controller for boost PFC applications that
operate in critical conduction mode (CRM). It uses a
voltage-mode PWM that compares an internal ramp
signal with the error amplifier output to generate a
MOSFET turn-off signal. Because the voltage-mode
CRM PFC controller does not need rectified AC line
voltage information, it saves the power loss of an input
voltage sensing network necessary for a current-mode
CRM PFC controller.
FAN7930B provides over-voltage protection, open-
feedback protection, over-current protection, input-
voltage-absent detection, and under-voltage lockout
protection. The additional OVP pin can be used to shut
down the boost power stage when output voltage
exceeds OVP level due to the resistors that are
connected at INV pin are damaged. The FAN7930B can
be disabled if the INV pin voltage is lower than 0.45V
and the operating current decreases to a very low level.
Using a new variable on-time control method, THD is
lower than the conventional CRM boost PFC ICs.
Applications
Adapter
Ballast
LCD TV, CRT TV
SMPS
Related Resources
AN-8035 — Design Consideration
Conduction Mode PFC Using FAN7930
for
Boundary
Ordering Information
Part Number
FAN7930BM
-40 to +125°C
FAN7930BMX
FAN7930B
8-Lead Small Outline Package (SOP)
Tape & Reel
Operating
Temperature
Range
Top Mark
Package
Packing
Method
Rail
© 2010 Fairchild Semiconductor Corporation
FAN7930B • Rev. 1.0.2
www.fairchildsemi.com
FAN7930B — Critical Conduction Mode PFC Controller
Application Diagram
Figure 1.
Typical Boost PFC Application
Internal Block Diagram
Figure 2.
Functional Block Diagram
© 2010 Fairchild Semiconductor Corporation
FAN7930B • Rev. 1.0.2
www.fairchildsemi.com
2
FAN7930B — Critical Conduction Mode PFC Controller
Pin Configuration
V
CC
OUT
GND
ZCD
FAN7930B
8-SOP
INV
Figure 3.
OVP COMP
CS
Pin Configuration (Top View)
Pin Definitions
Pin #
1
2
3
4
5
6
7
8
Name Description
INV
OVP
COMP
CS
ZCD
GND
OUT
V
CC
This pin is the inverting input of the error amplifier. The output voltage of the boost PFC converter
should be resistively divided to 2.5V.
This pin is used to detect PFC output over voltage when INV pin information is not correct.
This pin is the output of the transconductance error amplifier. Components for the output voltage
compensation should be connected between this pin and GND.
This pin is the input of the over-current protection comparator. The MOSFET current is sensed
using a sensing resistor and the resulting voltage is applied to this pin. An internal RC filter is
included to filter switching noise.
This pin is the input of the zero-current detection block. If the voltage of this pin goes higher than
1.5V, then goes lower than 1.4V, the MOSFET is turned on.
This pin is used for the ground potential of all the pins. For proper operation, the signal ground
and the power ground should be separated.
This pin is the gate drive output. The peak sourcing and sinking current levels are +500mA and -
800mA, respectively. For proper operation, the stray inductance in the gate driving path must be
minimized.
This is the IC supply pin. IC current and MOSFET drive current are supplied using this pin.
© 2010 Fairchild Semiconductor Corporation
FAN7930B • Rev. 1.0.2
www.fairchildsemi.com
3
FAN7930B — Critical Conduction Mode PFC Controller
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
V
CC
I
OH
, I
OL
I
CLAMP
I
DET
V
IN
T
J
T
A
T
STG
ESD
Supply Voltage
Peak Drive Output Current
Parameter
Min.
-800
-10
-10
(1)
Max.
V
Z
+500
+10
+10
8.0
6
+150
+125
+150
2.5
2.0
Unit
V
mA
mA
mA
V
°C
°C
°C
kV
Driver Output Clamping Diodes V
O
>V
CC
or V
O
<-0.3V
Detector Clamping Diodes
Error Amplifier Input, Output, OVP Input, ZCD and OVP Pin
CS Input Voltage
(2)
-0.3
-10
-40
-65
Operating Junction Temperature
Operating Temperature Range
Storage Temperature Range
Electrostatic Discharge
Capability
Human Body Model, JESD22-A114
Charged Device Model, JESD22-C101
Notes:
1. When this pin is supplied by external power sources by accident, its maximum allowable current is 50mA.
2. In case of DC input, acceptable input range is -0.3V~6V: within 100ns -10V~6V is acceptable, but electrical
specifications are not guaranteed during such a short time.
Thermal Impedance
Symbol
Θ
JA
Parameter
Thermal Resistance, Junction-to-Ambient
(3)
Min.
150
Max.
Unit
°C/W
Note:
3. Regarding the test environment and PCB type, please refer to JESD51-2 and JESD51-10.
© 2010 Fairchild Semiconductor Corporation
FAN7930B • Rev. 1.0.2
www.fairchildsemi.com
4
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