K7D163674B
K7D161874B
Document Title
16M DDR SYNCHRONOUS SRAM
512Kx36 & 1Mx18 SRAM
Revision History
Rev No.
Rev. 0.0
Rev. 0.1
History
Initial document.
Change JTAG DC OPERATING CONDITONS/AC TEST CONDITIONS
-to support 1.8~2.5V V
DD
, change some items.
Change DC CHARACTERISTICS (Stop Clock Standby Current)
-I
SB1
: 100 -> 150
Change JTAG Instruction Cording
- For Reserved
Change DC CHARACTERISTICS (Increase Operating Current)
- x36 : add 40mA, x18 : add 60mA
Draft Data
Oct. 2003
Nov. 2003
Remark
Advance
Preliminary
Rev. 0.2
Feb. 2004
Preliminary
Rev. 0.3
Feb. 2004
Preliminary
Rev. 1.0
Mar. 2004
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the
right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters
of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or cortact Headquarters.
-1-
Rev 1.0
Mar. 2004
K7D163674B
K7D161874B
FEATURES
512Kx36 or 1Mx18 Organizations.
1.8~2.5V V
DD
/1.5V V
DDQ
.(1.9V max V
DDQ
)
HSTL Input and Outputs.
Single Differential HSTL Clock.
Synchronous Pipeline Mode of Operation with Self-Timed
Late Write.
• Free Running Active High and Active Low Echo Clock Output
Pin.
• Asynchronous Output Enable.
•
•
•
•
•
512Kx36 & 1Mx18 SRAM
• Registered Addresses, Burst Control and Data Inputs.
• Registered Outputs.
• Double and Single Data Rate Burst Read and Write.
• Burst Count Controllable With Max Burst Length of 4
• Interleved and Linear Burst mode support
• Bypass Operation Support
• Programmable Impedance Output Drivers.
• JTAG Boundary Scan (subset of IEEE std. 1149.1)
• 153(9x17) Pin Ball Grid Array Package(14mmx22mm)
GENERAL DESCRIPTION
The K7D163674B and K7D161874B are 18,874,368 bit Synchronous Pipeline Burst Mode SRAM devices. They are organized as
524,288 words by 36 bits for K7D163674B and 1,048,576 words by 18 bits for K7D161874B, fabricated using Samsung's advanced
CMOS technology.
Single differential HSTL level clock, K and K are used to initiate the read/write operation and all internal operations are self-timed. At
the rising edge of K clock, all addresses and burst control inputs are registered internally. Data inputs are registered one cycle after
write addresses are asserted(Late Write), at the rising edge of K clock for single data rate (SDR) write operations and at rising and
falling edge of K clock for a double data rate (DDR) write operations.
Data outputs are updated from output registers off the rising edges of K clock for SDR read operations and off the rising and falling
edges of K clock for DDR read operations. Free running echo clocks are supported which are representive of data output access
time for all SDR and DDR operations.
The chip is operated with a single +2.5V power supply and is compatible with Extended HSTL input and output. The package is
9x17(153) Ball Grid Array balls on a 1.27mm pitch.
ORDERING INFORMATION
Part Number
K7D163674B-HC37
K7D163674B-HC33
K7D163674B-HC30
K7D163674B-HC27
K7D161874B-HC37
K7D161874B-HC33
K7D161874B-HC30
K7D161874B-HC27
1Mx18
512Kx36
Organization
Maximum
Frequency
375MHz
333MHz
300MHz
275MHz
375MHz
333MHz
300MHz
275MHz
-2-
Rev 1.0
Mar. 2004
K7D163674B
K7D161874B
FUNCTIONAL BLOCK DIAGRAM
SA[0:18]( or SA[0:19])
Address
Register
CE
19(or 20)
17(or 18)
(Burst Address)
Burst
Counter
(Burst Write
Address)
19(or 20)
17(or 18)
2:1
MUX
512Kx36 & 1Mx18 SRAM
Dec.
Data Out
K,K
Clock
Buffer
Memory Array
512Kx36
or
(1Mx18)
Data In
36(or18)x2
W/D
Array
36(or18)x2
Write Buffer
Comparator
B
1
B
3
Advance
Control
Co
SD/DD
Write
Address
Register
(2 stage)
CE
Synchronous
Select
&
R/W control
CE
R/W
LD
Internal
Clock
Generator
G
Data Output Strobe
Data Output Enable
State Machine
Strobe_out
36(or 18)x2
S/A Array
36(or 18)x2
2 : 1 MUX
B
2
Output
Buffer
Echo Clock
Output
Data In
Register
(2 stage)
36(or 18)
DQ
CQ,CQ
XDIN
PIN DESCRIPTION
Pin Name
K, K
SA
SA
0
, SA
1
DQ
CQ, CQ
B
1
B
2
B
3
G
LBO
Pin Description
Differential Clocks
Synchronous Address Input
Synchronous Burst Address Input (SA
0
= LSB)
Synchronous Data I/O
Differential Output Echo Clocks
Load External Address
Burst R/W Enable
Single/Double Data Selection
Asynchronous Output Enable
Linear Burst Order
Pin Name
ZQ
TCK
TMS
TDI
TDO
V
REF
V
DD
V
DDQ
V
SS
NC
Pin Description
Output Driver Impedance Control Input
JTAG Test Clock
JTAG Test Mode Select
JTAG Test Data Input
JTAG Test Data Output
HSTL Input Reference Voltage
Power Supply
Output Power Supply
GND
No Connection
-3-
Rev 1.0
Mar. 2004
K7D163674B
K7D161874B
PACKAGE PIN CONFIGURATIONS
(TOP VIEW)
K7D163674B(512Kx36)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
SS
DQ
V
SS
DQ
V
SS
DQ
V
SS
DQ
V
SS
DQ
V
SS
DQ
V
SS
DQ
V
SS
DQ
V
SS
2
V
DDQ
DQ
V
DDQ
DQ
V
DDQ
CQ
1
V
DDQ
DQ
V
DDQ
DQ
V
DDQ
CQ
1
V
DDQ
DQ
V
DDQ
DQ
V
DDQ
3
SA
SA
SA
SA
V
SS
DQ
V
SS
DQ
V
SS
DQ
V
SS
DQ
V
SS
NC
V
DD
SA
TMS
4
SA
V
SS
SA
V
SS
V
DD
V
DD
V
SS
V
DD
V
DD
V
SS
LBO
V
DD
V
DD
V
SS
SA
V
SS
TDI
5
ZQ
B
1
G
V
DD
V
REF
V
DD
K
K
V
DD
B
2
B
3
V
DD
V
REF
V
DD
SA
1
SA
0
TCK
512Kx36 & 1Mx18 SRAM
6
SA
V
SS
SA
V
SS
V
DD
V
DD
V
SS
V
DD
V
DD
V
SS
MODE
V
DD
V
DD
V
SS
SA
V
SS
TDO
7
SA
SA
SA
SA
V
SS
DQ
V
SS
DQ
V
SS
DQ
V
SS
DQ
V
SS
SA
V
DD
SA
NC
8
V
DDQ
DQ
V
DDQ
DQ
V
DDQ
CQ
2
V
DDQ
DQ
V
DDQ
DQ
V
DDQ
CQ
2
V
DDQ
DQ
V
DDQ
DQ
V
DDQ
9
V
SS
DQ
V
SS
DQ
V
SS
DQ
V
SS
DQ
V
SS
DQ
V
SS
DQ
V
SS
DQ
V
SS
DQ
V
SS
* Mode Pin(6L) is a internally NC.
K7D161874B(1Mx18)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
SS
NC
V
SS
DQ
V
SS
NC
V
SS
DQ
V
SS
NC
V
SS
DQ
V
SS
NC
V
SS
DQ
V
SS
2
V
DDQ
DQ
V
DDQ
NC
V
DDQ
CQ
1
V
DDQ
NC
V
DDQ
DQ
V
DDQ
NC
V
DDQ
DQ
V
DDQ
NC
V
DDQ
3
SA
SA
SA
SA
V
SS
NC
V
SS
DQ
V
SS
NC
V
SS
DQ
V
SS
SA
V
DD
SA
TMS
4
SA
V
SS
SA
V
SS
V
DD
V
DD
V
SS
V
DD
V
DD
V
SS
LBO
V
DD
V
DD
V
SS
SA
V
SS
TDI
5
ZQ
B
1
G
V
DD
V
REF
V
DD
K
K
V
DD
B
2
B
3
V
DD
V
REF
V
DD
SA
1
SA
0
TCK
6
SA
V
SS
SA
V
SS
V
DD
V
DD
V
SS
V
DD
V
DD
V
SS
MODE
V
DD
V
DD
V
SS
SA
V
SS
TDO
7
SA
SA
SA
SA
V
SS
DQ
V
SS
NC
V
SS
DQ
V
SS
NC
V
SS
SA
V
DD
SA
NC
8
V
DDQ
NC
V
DDQ
DQ
V
DDQ
NC
V
DDQ
DQ
V
DDQ
NC
V
DDQ
CQ
1
V
DDQ
NC
V
DDQ
DQ
V
DDQ
9
V
SS
DQ
V
SS
NC
V
SS
DQ
V
SS
NC
V
SS
DQ
V
SS
NC
V
SS
DQ
V
SS
NC
V
SS
* Mode Pin(6L)is a internally NC.
-4-
Rev 1.0
Mar. 2004
K7D163674B
K7D161874B
Read Operation(Single and Double)
512Kx36 & 1Mx18 SRAM
During SDR read operations, addresses and controls are registered at the first rising edge of K clock and then the internal array is
read between first and second rising edges of K clock. Data outputs are updated from output registers off the second rising edge of
K clock. During DDR read operations, addresses and controls are registered at the first rising edge of K clock, and then the internal
array is read twice between first and second rising edges of K clock. Data outputs are updated from output registers sequentially by
burst order off the second rising and falling edge of K clock.
Interleave and linear burst operation is controlled by LBO pin and the burst count is controllable with the maximum burst length of 4.
To avoid data contention,at least one NOP operations are required between the last read and the first write operation.
Write Operation(Late Write)
During SDR write operations, addresses and controls are registered at the first rising edge of K clock and data inputs are registered
at the following rising edge of K clock. During DDR write operations, addresses and controls are registered at the first rising edge of
K clock and data inputs are registered twice at the following rising and falling edge of K clock. Write addresses and data inputs are
stored in the data in registers until the next write operation, and only at the next write opeation are data inputs fully written into SRAM
array.
Echo clock operation
Free running type of Echo clocks are generated from K clock regardless of read, write and NOP operations. They will stop operation
only when K clock is in the stop mode.
Echo clocks are designed to represent data output access time and this allows the echo clocks to be used as reference to capture
data outputs outputs.
Bypass Read Operation
Bypass read operation occurs when the last write operation is followed by a read operation where write and read addresses are
identical. For this case, data outputs are from the data in registers instead of SRAM array.
Programmable Impedance Output Driver
The data output and echo clock driver impedance are adjusted by an external resistor, RQ, connected between ZQ pin and V
SS
, and
are equal to RQ/5. For example, 250Ω resistor will give an output impedance of 50Ω. Output driver impedance tolerance is 15% by
test(10% by design) and is periodically readjusted to reflect the changes in supply voltage and temperature. Impedance updates
occur early in cycles that do not activate the outputs, such as deselect cycles. They may also occur in cycles initiated with G high. In
all cases impedance updates are transparent to the user and do not produce access time "push-outs" or other anomalous behavior
in the SRAM. Impedance updates occur no more often than every 32 clock cycles. Clock cycles are counted whether the SRAM is
selected or not and proceed regardless of the type of cycle being executed. Therefore, the user can be assured that after 33 contin-
uous read cycles have occurred, an impedance update will occur the next time G are high at a rising edge of the K clock. There are
no power up requirements for the SRAM. However, to guarantee optimum output driver impedance after power up, the SRAM needs
1024 non-read cycles.
Power-Up/Power-Down Supply Voltage Sequencing
The following power-up supply voltage application is recommended: V
SS
, V
DD
, V
DDQ
, V
REF
, then V
IN
. V
DD
and V
DDQ
can be applied
simultaneously, as long as V
DDQ
does not exceed V
DD
by more than 0.5V during power-up. The following power-down supply voltage
removal sequence is recommended: V
IN
, V
REF
, V
DDQ
, V
DD
, V
SS
. V
DD
and V
DDQ
can be removed simultaneously, as long as V
DDQ
does not exceed V
DD
by more than 0.5V during power-down.
-5-
Rev 1.0
Mar. 2004
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