K7D161888M-HC300 datasheet, PDF

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K7D161888M-HC300: DescriptionDDR SRAM, 1MX18, CMOS, PBGA153, 14 X 22 MM, BGA-153; Categorystorage storage; File Size169KB，16 Pages; ManufacturerSAMSUNG; Websitehttp://www.samsung.com/Products/Semiconductor/

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K7D161888M-HC300 Overview

DDR SRAM, 1MX18, CMOS, PBGA153, 14 X 22 MM, BGA-153

K7D161888M-HC300 Parametric

Parameter Name	Attribute value
Maker	SAMSUNG
Parts packaging code	BGA
package instruction	BGA,
Contacts	153
Reach Compliance Code	unknown
ECCN code	3A991.B.2.A
Other features	PIPELINED ARCHITECTURE
JESD-30 code	R-PBGA-B153
length	22 mm
memory density	18874368 bit
Memory IC Type	DDR SRAM
memory width	18
Number of functions	1
Number of terminals	153
word count	1048576 words
character code	1000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	1MX18
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Package shape	RECTANGULAR
Package form	GRID ARRAY
Parallel/Serial	PARALLEL
Certification status	Not Qualified
Maximum seat height	2.21 mm
Maximum supply voltage (Vsup)	1.9 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
width	14 mm

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K7D161888B

Document Title

16M DDR SYNCHRONOUS SRAM

Advance

1Mx18 SRAM

Revision History

Rev No.

Rev. 0.0

Rev. 0.1

History

Initial document.

Remove K7D163688B

Draft Data

Feb. 2003

Jun. 2003

Remark

Advance

The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the

right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters

of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or cortact Headquart ers.

-1-

Rev 0.1

Jun. 2003

K7D161888B

Read Operation(Single and Double)

Advance

1Mx18 SRAM

During SDR read operations, addresses and controls are registered at the first rising edge of K clock and then the internal array is

read between first and second rising edges of K clock. Data outputs are updated from output registers off the second rising edge of

K clock. During DDR read operations, addresses and controls are registered at the first rising edge of K clock, and then the internal

array is read twice between first and second rising edges of K clock. Data outputs are updated from output registers sequentially by

burst order off the second rising and falling edge of K clock.

Interleave and linear burst operation is controlled by LBO pin and the burst count is controllable with the maximum burst length of 4.

To avoid data contention,at least one NOP operations are required between the last read and the first write operation.

Write Operation(Late Write)

During SDR write operations, addresses and controls are registered at the first rising edge of K clock and data inputs are regis tered

at the following rising edge of K clock. During DDR write operations, addresses and controls are registered at the first rising edge of

K clock and data inputs are registered twice at the following rising and falling edge of K clock. Write addresses and data inputs are

stored in the data in registers until the next write operation, and only at the next write opeation are data inputs fully written into SRAM

array.

Echo clock operation

Free running type of Echo clocks are generated from K clock regardless of read, write and NOP operations. They will stop operation

only when K clock is in the stop mode.

Echo clocks are designed to represent data output access time and this allows the echo clocks to be used as reference to capture

data outputs outputs.

Bypass Read Operation

Bypass read operation occurs when the last write operation is followed by a read operation where write and read addresses are

identical. For this case, data outputs are from the data in registers instead of SRAM array.

Programmable Impedance Output Driver

The data output and echo clock driver impedance are adjusted by an external resistor, RQ, connected between ZQ pin and V

, and

are equal to RQ/5. For example, 250Ω resistor will give an output impedance of 50Ω. Output driver impedance tolerance is 15% by

test(10% by design) and is periodically readjusted to reflect the changes in supply voltage and temperature. Impedance updates

occur early in cycles that do not activate the outputs, such as deselect cycles. They may also occur in cycles initiated with G high. In

all cases impedance updates are transparent to the user and do not produce access time "push-outs" or other anomalous behavior

in the SRAM. Impedance updates occur no more often than every 32 clock cycles. Clock cycles are counted whether the SRAM is

selected or not and proceed regardless of the type of cycle being executed. Therefore, the user can be assured that after 33 contin-

uous read cycles have occurred, an impedance update will occur the next time G are high at a rising edge of the K clock. There are

no power up requirements for the SRAM. However, to guarantee optimum output driver impedance after power up, the SRAM needs

1024 non-read cycles.

-5-

Rev 0.1

Jun. 2003

K7D161888M-HC300 Related Products

	K7D161888M-HC300	K7D161888M-HC330	K7D161888M-HC370	K7D161888M-HC250
Description	DDR SRAM, 1MX18, CMOS, PBGA153, 14 X 22 MM, BGA-153	DDR SRAM, 1MX18, CMOS, PBGA153, 14 X 22 MM, BGA-153	DDR SRAM, 1MX18, CMOS, PBGA153, 14 X 22 MM, BGA-153	DDR SRAM, 1MX18, CMOS, PBGA153, 14 X 22 MM, BGA-153
Maker	SAMSUNG	SAMSUNG	SAMSUNG	SAMSUNG
Parts packaging code	BGA	BGA	BGA	BGA
package instruction	BGA,	BGA,	BGA,	BGA,
Contacts	153	153	153	153
Reach Compliance Code	unknown	unknown	unknown	unknown
ECCN code	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A
Other features	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE
JESD-30 code	R-PBGA-B153	R-PBGA-B153	R-PBGA-B153	R-PBGA-B153
length	22 mm	22 mm	22 mm	22 mm
memory density	18874368 bit	18874368 bit	18874368 bit	18874368 bit
Memory IC Type	DDR SRAM	DDR SRAM	DDR SRAM	DDR SRAM
memory width	18	18	18	18
Number of functions	1	1	1	1
Number of terminals	153	153	153	153
word count	1048576 words	1048576 words	1048576 words	1048576 words
character code	1000000	1000000	1000000	1000000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	70 °C	70 °C	70 °C	70 °C
organize	1MX18	1MX18	1MX18	1MX18
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	BGA	BGA	BGA	BGA
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY
Parallel/Serial	PARALLEL	PARALLEL	PARALLEL	PARALLEL
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	2.21 mm	2.21 mm	2.21 mm	2.21 mm
Maximum supply voltage (Vsup)	1.9 V	1.9 V	1.9 V	1.9 V
Minimum supply voltage (Vsup)	1.7 V	1.7 V	1.7 V	1.7 V
Nominal supply voltage (Vsup)	1.8 V	1.8 V	1.8 V	1.8 V
surface mount	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal form	BALL	BALL	BALL	BALL
Terminal pitch	1.27 mm	1.27 mm	1.27 mm	1.27 mm
Terminal location	BOTTOM	BOTTOM	BOTTOM	BOTTOM
width	14 mm	14 mm	14 mm	14 mm

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