Operated at Commercial and Industrial Temperature Ranges.
CMOS SRAM
Revision History
Rev No.
Rev. 0.0
Rev. 1.0
History
Initial release with Design Target.
Release to Preliminary Data Sheet.
1.1. Replace Design Target to Preliminary.
Release to Final Data Sheet.
2.1. Delete Preliminary.
2.2. Add 30pF capacitive in test load.
2.3. Relax DC characteristics.
Item
Previous
I
CC
10ns
170mA
12ns
160mA
15ns
150mA
I
SB
f=max.
40mA
I
SB1
f=0
10 / 1mA
I
DR
V
DR
=3.0V
0.9mA
Draft Data
Jan. 1st, 1997
Jun. 1st, 1997
Remark
Design Target
Preliminary
Rev. 2.0
Feb.11th.1998
Final
Current
205mA
200mA
195mA
50mA
10 / 1.2mA
1.0mA
Jun.27th 1998
Final
Rev. 2.1
Change operating current at Industrial Temperature range.
Previous spec.
Changed spec.
Items
(10/12/15ns part)
(10/12/15ns part)
Icc
205/200/195mA
230/225/220mA
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-1-
Rev 2.1
June 1998
PRELIMINARY
KM68V4002B/BL, KM68V4002BI/BLI
512K x 8 Bit High-Speed CMOS Static RAM(3.3V Operating)
FEATURES
• Fast Access Time 10,12,15ns(Max.)
• Low Power Dissipation
Standby (TTL)
: 50mA(Max.)
(CMOS) : 10mA(Max.)
1.2mA(Max.)- L-Ver.
Operating KM68V4002B/BL - 10 : 205mA(Max.)
KM68V4002B/BL - 12 : 200mA(Max.)
KM68V4002B/BL - 15 : 195mA(Max.)
• Single 3.3
±0.3V
Power Supply
• TTL Compatible Inputs and Outputs
• Fully Static Operation
- No Clock or Refresh required
• Three State Outputs
• 2V Minimum Data Retention ; L-Ver. only
• Center Power/Ground Pin Configuration
• Standard Pin Configuration
KM68V4002BJ : 36-SOJ-400
KM68V4002BT : 36-TSOP2-400F
CMOS SRAM
GENERAL DESCRIPTION
The KM68V4002B is a 4,194,304-bit high-speed Static Ran-
dom Access Memory organized as 524,288 words by 8 bits.
The KM68V4002B uses 8 common input and output lines and
has an output enable pin which operates faster than address
access time at read cycle. The device is fabricated using SAM-
SUNG′s advanced CMOS process and designed for high-
speed circuit technology. It is particularly well suited for use in
high-density
high-speed
system
applications.
The
KM68V4002B is packaged in a 400 mil 36-pin plastic SOJ or
TSOP(II) forward.
PIN CONFIGURATION
(Top View)
A
0
A
1
A
2
1
2
3
4
5
6
7
8
9
10
36 N.C
35 A
18
34 A
17
33 A
16
32 A
15
31 OE
30 I/O
8
ORDERING INFORMATION
KM68V4002B/BL -10/12/15
KM68V4002BI/BLI -10/12/15
Commercial Temp.
Industrial Temp.
A
3
A
4
CS
I/O
1
I/O
2
FUNCTIONAL BLOCK DIAGRAM
Clk Gen.
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
I/O
1
~I/O
8
Vcc
Vss
SOJ/
TSOP2
29 I/O
7
28 Vss
27 Vcc
26 I/O
6
25 I/O
5
24 A
14
23 A
13
22 A
12
21 A
11
20 A
10
19 N.C
Pre-Charge Circuit
I/O
3
11
I/O
4
12
WE
A
5
13
14
15
16
17
18
Row Select
Memory Array
512 Rows
1024x8 Columns
A
6
A
7
A
8
A
9
Data
Cont.
CLK
Gen.
I/O Circuit
Column Select
PIN FUNCTION
Pin Name
A
0
- A
18
WE
Pin Function
Address Inputs
Write Enable
Chip Select
Output Enable
Data Inputs/Outputs
Power(+3.3V)
Ground
No Connection
A
10
A
12
A
14
A
16
A
18
A
9
A
11
A
13
A
15
A
17
CS
OE
CS
WE
OE
I/O
1
~ I/O
8
V
CC
V
SS
N.C
-2-
Rev 2.1
June 1998
PRELIMINARY
KM68V4002B/BL, KM68V4002BI/BLI
ABSOLUTE MAXIMUM RATINGS*
Parameter
Voltage on Any Pin Relative to V
SS
Voltage on V
CC
Supply Relative to V
SS
Power Dissipation
Storage Temperature
Operating Temperature
Commercial
Industrial
Symbol
V
IN
, V
OUT
V
CC
P
D
T
STG
T
A
T
A
Rating
-0.5 to 4.6
-0.5 to 4.6
1.0
-65 to 150
0 to 70
-40 to 85
Unit
V
V
W
°C
°C
°C
CMOS SRAM
*
Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS*
(T
A
=0 to 70°C)
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Symbol
V
CC
V
SS
V
IH
V
IL
Min
3.0
0
2.0
-0.3**
Typ
3.3
0
-
-
Max
3.6
0
V
CC
+0.3***
0.8
Unit
V
V
V
V
* The above parameters are also guaranteed at industrial temperature range.
** V
IL
(Min) = -2.0V a.c(Pulse Width
≤
8ns) for I
≤
20mA.
*** V
IH
(Max) = V
CC +
2.0V a.c (Pulse Width
≤
8ns) for I
≤
20mA.
DC AND OPERATING CHARACTERISTICS*
(T
A
=0 to 70°C, Vcc=3.3±0.3V, unless otherwise specified)
Parameter
Input Leakage Current
Output Leakage Current
Operating Current
Symbol
I
LI
I
LO
I
CC
V
IN
=V
SS
to V
CC
CS=V
IH
or OE=V
IH
or WE=V
IL
V
OUT
=V
SS
to V
CC
Min. Cycle, 100% Duty
CS=V
IL,
V
IN
=V
IH
or V
IL,
I
OUT
=0mA
10ns
12ns
15ns
Standby Current
I
SB
I
SB1
Min. Cycle, CS=V
IH
f=0MHz, CS≥V
CC
-0.2V,
V
IN
≥V
CC
-0.2V or V
IN
≤
0.2V
I
OL
=8mA
I
OH
=-4mA
Normal
L-Ver.
Test Conditions
Min
-2
-2
-
-
-
-
-
-
-
2.4
Max
2
2
205
200
195
50
10
1.2
0.4
-
V
V
mA
mA
Unit
µA
µA
mA
Output Low Voltage Level
Output High Voltage Level
V
OL
V
OH
* The above parameters are also guaranteed at industrial temperature range.
CAPACITANCE*
(T
A
=25°C, f=1.0MHz)
Item
Input/Output Capacitance
Input Capacitance
* Capacitance is sampled and not 100% tested.
Symbol
C
I/O
C
IN
Test Conditions
V
I/O
=0V
V
IN
=0V
MIN
-
-
Max
8
7
Unit
pF
pF
-3-
Rev 2.1
June 1998
PRELIMINARY
KM68V4002B/BL, KM68V4002BI/BLI
AC CHARACTERISTICS
(T
A
=0 to 70°C, V
CC
=3.3±0.3V, unless otherwise noted.)
TEST CONDITIONS*
Parameter
Input Pulse Levels
Input Rise and Fall Times
Input and Output timing Reference Levels
Output Loads
* The above test conditions are also applied at industrial temperature range.
CMOS SRAM
Value
0V to 3V
3ns
1.5V
See below
Output Loads(A)
Output Loads(B)
for t
HZ
, t
LZ
, t
WHZ
, t
OW
, t
OLZ
& t
OHZ
+3.3V
R
L
= 50Ω
D
OUT
V
L
= 1.5V
Z
O
= 50Ω
30pF*
319Ω
D
OUT
353Ω
5pF*
* Capacitive Load consists of all components of the
test environment.
* Including Scope and Jig Capacitance
READ CYCLE*
Parameter
Read Cycle Time
Address Access Time
Chip Select to Output
Output Enable to Valid Output
Chip Enable to Low-Z Output
Output Enable to Low-Z Output
Chip Disable to High-Z Output
Output Disable to High-Z Output
Output Hold from Address Change
Chip Selection to Power Up Time
Chip Selection to Power DownTime
Sym-
bol
t
RC
t
AA
t
CO
t
OE
t
LZ
t
OLZ
t
HZ
t
OHZ
t
OH
t
PU
t
PD
KM68V4002B/BL-10
Min
10
-
-
-
3
0
0
0
3
0
-
Max
-
10
10
5
-
-
5
5
-
-
15
KM68V4002B/BL-12
Min
12
-
-
-
3
0
0
0
3
0
-
Max
-
12
12
6
-
-
6
6
-
-
12
KM68V4002B/BL-15
Min
15
-
-
-
3
0
0
0
3
0
-
Max
-
15
15
7
-
-
7
7
-
-
15
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
* The above parameters are also guaranteed at industrial temperature range.
-4-
Rev 2.1
June 1998
PRELIMINARY
KM68V4002B/BL, KM68V4002BI/BLI
WRITE CYCLE*
Parameter
Write Cycle Time
Chip Select to End of Write
Address Set-up Time
Address Valid to End of Write
Write Pulse Width(OE High)
Write Pulse Width(OE Low)
Write Recovery Time
Write to Output High-Z
Data to Write Time Overlap
Data Hold from Write Time
End Write to Output Low-Z
Symbol
t
WC
t
CW
t
AS
t
AW
t
WP
t
WP1
t
WR
t
WHZ
t
DW
t
DH
t
OW
KM68V4002B/BL-10
Min
10
7
0
7
7
10
0
0
5
0
3
Max
-
-
-
-
-
-
-
5
-
-
-
KM68V4002B/BL-12
Min
12
8
0
8
8
12
0
0
6
0
3
Max
-
-
-
-
-
-
-
6
-
-
-
KM68V4002B/BL-15
Min
15
10
0
10
10
15
0
0
7
0
3
Max
-
-
-
-
-
-
-
7
-
-
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CMOS SRAM
* The above parameters are also guaranteed at industrial temperature range.
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