DATA SHEET
µ
PD77110, 77111, 77112
16-BIT FIXED-POINT DIGITAL SIGNAL PROCESSORS
MOS INTEGRATED CIRCUIT
DESCRIPTION
The
µ
PD77110, 77111, and 77112 are 16-bit fixed-point digital signal processors (DSPs).
Compared with the
µ
PD77016 family, these DSPs have improved power consumption and are ideal for battery-
powered mobile terminals such as PDAs and cellular phones.
Both mask ROM and RAM models are available.
For details of the functions of these DSPs, refer to the following User’s Manuals:
µ
PD77111 Family User’s Manual
: To be available soon
µ
PD7701X Family User’s Manual - Instructions: U13116E
FEATURES
z
Instruction cycle (operating clock)
µ
PD77110 : 15.3 ns MIN (65 MHz MAX)
13.3 ns MIN (75 MHz MAX) (Operating voltage and ambient temperature are limited.)
µ
PD77111 : 13.3 ns MIN (75 MHz MAX)
µ
PD77112 : 13.3 ns MIN (75 MHz MAX)
z
Memory
• Internal instruction memory
µ
PD77110 : RAM 35.5K words
×
32 bits
µ
PD77111 : RAM 1K words
×
32 bits
Mask ROM 31.75K words
×
32 bits
µ
PD77112 : RAM 1K words
×
32 bits
Mask ROM 31.75K words
×
32 bits
• Data memory
µ
PD77110 : RAM 24K words
×
16 bits
×
2 banks
External memory space 32K words
×
16 bits
×
2 banks
µ
PD77111 : RAM 3K words
×
16 bits
×
2 banks
Mask ROM 16K words
×
16 bits
×
2 banks
µ
PD77112 : RAM 3K words
×
16 bits
×
2 banks
Mask ROM 16K words
×
16 bits
×
2 banks
External memory space 16K words
×
16 bits
×
2 banks
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. U12801EJ4V0DS00 (4th edition)
Date Published November 1999 N CP(K)
Printed in Japan
The mark
shows major revised points.
©
1998, 1999
µ
PD77110, 77111, 77112
ORDERING INFORMATION
Part Number
Package
100-pin plastic TQFP (fine pitch) (14
×
14 mm)
80-pin plastic TQFP (fine pitch) (12
×
12 mm)
80-pin plastic fine-pitch BGA (9
×
9 mm)
100-pin plastic TQFP (fine pitch) (14
×
14 mm)
µ
PD77110GC-9EU
µ
PD77111GK-xxx-9EU
µ
PD77111F1-xxx-CN1
µ
PD77112GC-xxx-9EU
Remark
xxx indicates ROM code suffix.
2
Data Sheet U12801EJ4V0DS00
BLOCK DIAGRAM
X bus
External memory
Y bus
Peripheral units
R0 - R7
Serial
I/O #1
X memory
Y memory
X memory
data
addressing
unit
Y memory
data
addressing
unit
Data memory unit
Serial
I/O #2
Main bus
MPY
16
×
16 + 40
→
40
ALU (40)
BSFT
Port
Program
control unit
Data Sheet U12801EJ4V0DS00
Loop control
stack
PC stack
Instruction
memory
Host I/O
CPU control
PLL
Interrupt
control
Operation unit
Wait
controller
RESET WAKEUP
Note 1
CLKOUT
CLKIN
INT1 - INT4
Note 1
PLL0 - PLL2
Note 2
Notes 1.
The WAKEUP pin is multiplexed with the INT4 pin. With the
µ
PD77111 and 77112, the function of the WAKEUP pin can be
IE
I/O
activated or deactivated by mask option. With the
µ
PD77110, this function is always valid.
2.
These pins are provided only on the
µ
PD77110. The PLL0 and PLL1 pins are multiplexed with the P2 and P3 pins.
µ
PD77110, 77111, 77112
3
µ
PD77110, 77111, 77112
PIN CONFIGURATION
+2.5 V
+3 V
Serial interface #1
SO1
SORQ1
SOEN1
SCK1
SI1
SIEN1
SIAK1
SO2
SOEN2
SCK2
SI2
SIEN2
(4)
P0 - P3
IV
DD
EV
DD
RESET
INT1 - INT4
CLKIN
CLKOUT
Reset, interrupt
(4)
Clock
PLL0 - PLL2
Note 1
WAKEUP
Note 2
(3)
System control
Serial interface #2
Port
(2)
Host interface
(8)
For debugging
(2)
(4)
HCS
HA0, HA1
HRD
HRE
HWR
HWE
HD0 - HD7
DA0 - DA14
Note 3
X/Y
D0 - D15
MRD
MWR
HOLDRQ
HOLDAK
BSTB
(15)
External data
(16) memory
Note 4
Data bus
control
TDO, TICE
TCK, TDI, TMS, TRST
GND
Notes 1.
These pins are provided only on the
µ
PD77110.
2.
With the
µ
PD77111 and 77112, the function of this pin can be activated or deactivated by mask option.
With the
µ
PD77110, this function is always valid.
3.
DA14 is not provided on the
µ
PD77112.
4.
An external data memory interface is not provided on the
µ
PD77111.
4
Data Sheet U12801EJ4V0DS00
DSP FUNCTION LIST
µ
PD77018A
256
×
32
24K
×
32
None
24K
×
16 each
3K
×
16 each
3K
×
16 each
31.75K
×
32
48K
×
32
16K
×
16 each
4K
×
32
35.5K
×
32
1K
×
32
3.5K
×
32
Item
µ
PD77016
µ
PD77019
µ
PD77019-013
µ
PD77110
µ
PD77111
µ
PD77112
µ
PD77113
µ
PD77114
1.5K
×
32
Memory space Internal instruction RAM
(words
×
bits)
Internal instruction ROM
None
Data RAM
(X/Y memory)
12K
×
16 each
None
16K
×
16 each
2K
×
16 each
Data ROM
(X/Y memory)
None
None
32K
×
16 each
External instruction
48K
×
32
memory
16K
×
16 each
None
32K
×
16 each
16K
×
16 each
None
8K
×
16 each
External data memory
(X/Y memory)
16.6 ns (60 MHz)
×1,
2, 3, 4, 8 (mask option)
(external pin)
Fixed to
×4
Integer of
×1
to 8
15.3 ns (65 MHz)
48K
×
16 each
Instruction cycle (at maximum speed)
30 ns (33 MHz)
13.3 ns (75 MHz)
Integer of
×1
to 16 (mask option)
Multiple
–
Serial interface (two channels)
Channels 1 and 2
Channel 1 has same function as
µ
PD77016. Channel 2 does not have SORQ2 and SIAK2 pins (for connection of codec).
Data Sheet U12801EJ4V0DS00
have same function.
3V
DSP core: 2.5 V
I/O pins : 3 V
80-pin TQFP
80-pin FBGA
100-pin TQFP
80-pin FBGA
100-pin TQFP
Supply voltage
5V
Package
160-pin QFP
100-pin TQFP
116-pin BGA
100-pin TQFP
µ
PD77110, 77111, 77112
5