PRELIMINARY DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD77019-013
16 bits, Fixed-point Digital Signal Processor
The
µ
PD77019-013 is a masked 16 bits fixed-point DSP (Digital Signal Processor) developed for digital signal
processing with its demand for high speed and precision.
The
µ
PD77019-013 internal ROM area is masked already by the void code to use as RAM based DSP without mask
code ordering process. Also the
µ
PD77019-013 can operate as simplified evaluate chip for as the
µ
PD7701x family.
About mask ROM and mask option, there are following differences between the
µ
PD77019-013 and
µ
PD77019.
µ
PD77019-013
PLL clock multiple rate
Fixed to 4
µ
PD77019
Variable multiple rate (1, 2, 3, 4, 8) by mask
option
Enable (PLL clock multiple rate is set to 1 by
mask option.)
Crystal resonator
connection
Clock Input pin
Disable (PLL clock multiple rate is fixed to 4.)
External clock is connected to the X1 pin.
Leave the X2 pin open.
External clock is connected to the X1 pin.
Crystal is connected between the X1 pin and
X2 pin.
Low level fixed, or internal system clock
output is selectable by mask option.
Coding user program or data when ordering
mask ROM.
Enable to boot from internal data ROM or
external data area.
Clock output pin
Output internal system clock.
Internal mask ROM
Self boot
Not available (already masked by the void
code)
Enable to boot from external data area (Boot
information data is masked.) Refer to
2.6
Boot Function.
ORDERING INFORMATION
Part Number
Package
100-pin plastic TQFP (FINE PITCH) (14
×
14 mm)
µ
PD77019GC-013-9EU
The
µ
PD7701x family consists of the
µ
PD77016, 77015, 77017, 77018, 77018A and
µ
PD77019.
The information in this document is subject to change without notice.
Document No. U13053EJ1V0DS00 (1st edition)
Date Published March 1998 N CP(K)
Printed in Japan
©
1998
µ
PD77019-013
FEATURES
•
FUNCTIONS
• Instruction cycle: 16.6 ns (MIN.)
Operation clock: 60 MHz
External clock: 15 MHz
• Dual load/store
• Hardware loop function
• Conditional execution
• Executes product-sum operation in one instruction cycle
•
PROGRAMMING
• 16 bits
×
16 bits + 40 bits
→
40 bits multiply accumulator
• 8 general registers (40 bits each)
• 8 ROM/RAM data pointer: each data memory area has 4 registers
• 10 source interrupts (external: 4, internal: 6)
• 3 operand instructions (example: R0 = R0 +R1L∗R2L)
• Nonpipeline on execution stage
•
MEMORY AREAS
• Instruction memory area : 64K words
×
32 bits
• Data memory areas : 64K words
×
16 bits
×
2 (X memory, Y memory)
•
CLOCK GENERATOR
• On-chip PLL to provide higher operation clock (60 MHz max.) than the external clock. PLL clock multiple rate is
fixed to 4.
•
ON-CHIP PERIPHERAL
• I/O port: 4 bits
• Serial I/O (16 bits): 2 channels
• Host I/O (8 bits): 1 channel
•
CMOS
•
+3 V single power supply
2
Preliminary Data Sheet
Functional Differences among the
µ
PD7701× Family
µ
PD77015
µ
PD77017
µ
PD77018
µ
PD77018A
µ
PD77019
µ
PD77019-013
4K words
24K words
None
1K words each
2K words each
16K words each
30 ns (33 MHz)
16.6 ns (60 MHz)
4K words each
12K words each
2K words each
3K words each
None
None
256 words
4K words
12K words
Item
µ
PD77016
Internal instruction RAM
1.5K words
Internal instruction ROM
None
External instruction memory
48K words
Data RAM (X/Y memory)
2K words each
Data ROM (X/Y memory)
None
External data memory
48K words each
Instruction cycle
(Maximum operation speed)
External clock
(at maximum operation speed)
33/16.5/8.25/4.125 MHz
Variable multiple rate (1, 2, 4, 8 ) by mask option.
66 MHz
60/30/20/15/7.5 MHz
Variable multiple rate (1, 2, 3, 4, 8 ) by
mask option.
60 MHz
15 MHz
Multiple rate is
fixed to 4.
–
Crystal
(at maximum operation speed)
33 MHz
–
Instruction
–
STOP instruction is added.
Channel 1 has the same functions as that of the
µ
PD77016.
Channel 2 has no SORQ2 or SIAK2 pin (Channel 2 is used for CODEC connection).
3V
100-pin plastic TQFP
100-pin plastic TQFP
116-pin plastic BGA
100-pin plastic TQFP
Preliminary Data Sheet
Serial interface (2 Channels)
Channel 1 has the
same functions
as channel 2.
Power supply
5V
Package
160-pin plastic QFP
µ
PD77019-013
5
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