DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD77015,77017,77018
16 bits, Fixed-point Digital Signal Processor
µ
PD77015, 77017, 77018 are 16 bits fixed-point DSPs (Digital Signal Processors) developed for digital signal
processing with its demand for high speed and precision.
FEATURES
•
FUNCTIONS
• Instruction cycle: 30 ns (MIN.)
Operation clock: 33 MHz
External clock: 33, 16.5, 8.25, 4.125 MHz
Crystal: 33 MHz
• On-chip PLL to provide higher operation clock than the external clock
• Dual load/store
• Hardware loop function
• Conditional execution
• Executes product-sum operation in one instruction cycle
•
PROGRAMMING
• 16 bits
×
16 bits + 40 bits
→
40 bits multiply accumulator
• 8 general registers (40 bits each)
• 8 ROM/RAM data pointer: each data memory area has 4 registers
• 10 source interrupts (external: 4, internal: 6)
• 3 operand instructions (example: R0 = R0 +R1L∗R2L)
• Nonpipeline on execution stage
•
MEMORY AREAS
• Instruction memory area : 64K words
×
32 bits
• Data memory areas : 64K words
×
16 bits
×
2 (X memory, Y memory)
•
CLOCK GENERATOR
• Mask option for CLKOUT pin:
Fixed to the low level.
Does not output the internal system clock.
• Selectable source clock: external clock input and crystal resonator
[External clock]
On-chip PLL to provide higher operation clock (33 MHz MAX.) than the external clock.
Variable multiple rates (1, 2, 4, 8) by mask option.
[Crystal resonator]
Oscillation frequency corresponds directly to the system clock frequency (Sure to specify the mask option
frequency multiple as "1").
In this document, all descriptions of the
µ
PD77017 also apply to the
µ
PD77015 and
µ
PD77018, unless
otherwise specified.
The information in this document is subject to change without notice.
Document No. U10902EJ3V0DS00 (3rd edition)
Date Published June 1997 N
Printed in Japan
The mark
shows major revised points.
©
1993, 1994
Functional Differences among the
µ
PD7701× Family
µ
PD77015
µ
PD77017
µ
PD77018
µ
PD77018A
µ
PD77019
4K words
24K words
None
1K words each
2K words each
16K words each
30 ns (33 MHz)
19 ns (52 MHz)
4K words each
12K words each
2K words each
3K words each
256 words
4K words
12K words
Item
µ
PD77016
Internal instruction RAM
None
1.5K words
Internal instruction ROM
External instruction memory
48K words
Data RAM (X/Y memory)
None
2K words each
Data ROM (X/Y memory)
External data memory
48K words each
Instruction cycle
(Maximum operation speed)
66 MHz
External clock
33/16.5/8.25/4.125 MHz
Variable multiple rate (1, 2, 4, 8 ) by mask option.
(at maximum operation speed)
52/ 26/ 17.333/ 13/6.5 MHz
Variable multiple rate (1, 2, 3, 4, 8 ) by
mask option.
52 MHz
Crystal
(at maximum operation speed)
–
33 MHz
–
Instruction
STOP instruction is added.
Channel 1 has the same functions as that of the
µ
PD77016.
Channel 2 has no SORQ2 or SIAK2 pin (Channel 2 is used for CODEC connection).
3V
Serial interface (2 Channels)
Channel 1 has the
same functions
as channel 2.
5V
Power supply
µ
PD77015, 77017, 77018
Package
160-pin plastic QFP
100-pin plastic TQFP
5
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