STK17TA8
nvTime™
Event Data Recorder
128K x 8
AutoStore™
nvSRAM
with Real-Time Clock
Product Preview
FEATURES
• Data Integrity of Simtek nvSRAM Combined
with Full-Featured Real-Time Clock
• 25ns, 35ns and 45ns Access Times
• Software or
AutoStore™STORE
to
Quan-
tumTrap™
Nonvolatile Elements
•
RECALL
to SRAM Initiated by Software or
Power Restore
• Unlimited READ, WRITE and
RECALL
Cycles
• 100-Year Data Retention
• Watchdog Timer
• Clock Alarm with programmable Interrupts
• Capacitor or battery backup for RTC
• Single 3V +20%, -10% Operation
• Commercial and Industrial Temperatures
• Packages: 48 pin SSOP, 40 pin DIP
DESCRIPTION
The Simtek STK17TA8 combines a 1 Mbit nonvola-
tile static RAM with a full-featured real-time clock in
a reliable, monolithic integrated circuit. The embed-
ded nonvolatile elements incorporate Simtek’s
QuantumTrap™
technology producing the world’s
most reliable nonvolatile memory. The
SRAM
can be
read and written an unlimited number of times, while
independent, nonvolatile data resides in the nonvol-
atile elements.
The Real-Time Clock function provides an accurate
clock with leap year tracking and a programmable,
high accuracy oscillator. The Alarm function is pro-
grammable for one-time alarms or periodic seconds,
minutes, hours, or days. There is also a programma-
ble Watchdog Timer for process control.
BLOCK DIAGRAM
HSB
Quantum Trap
1024 x 1024
ROW DECODER
V
CCX
V
CAP
V
rtcbat
V
rtccap
A
5
A
6
A
7
A
8
A
9
A
12
A
13
A
14
A
15
A
16
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
STORE
STATIC RAM
ARRAY
1024 x 1024
RECALL
STORE/
RECALL
CONTROL
POWER
CONTROL
SOFTWARE
DETECT
A
0
- A
16
INPUT BUFFERS
COLUMN I/O
COLUMN DEC
RTC
X
1
X
2
INT
A
0
A
1
A
2
A
3
A
4
A
10
A
11
MUX
A
0
-
A
16
G
E
W
February 2004
1
Document Control # ML0023 rev 0.3
STK17TA8
PACKAGES
48 Pin 300 mil SSOP
(not to scale)
40 Pin 600 mil DIP
PIN DESCRIPTIONS
Pin Name
A
0
- A
16
DQ
0
-DQ
7
E
W
G
X
1
, X
2
V
rtccap
V
rtcbat
V
CCX
HSB
INT
I/O
Input
I/O
Input
Input
Input
Input
Power Supply
Power Supply
Power Supply
I/O
Output
Description
Address: The 17 address inputs select one of 131,072 bytes in the
nvSRAM array or one of 16 bytes in the clock register map.
Data: Bi-directional 8-bit data bus for accessing the nvSRAM array and
clock.
Chip Enable: The active low E input selects the device.
Write Enable: The active low W enables data on the DQ pins to be
written to the adddress location latched by the falling edge of E.
Output Enable: The active low G input enables the data output buffers
during read cycles. Deasserting G high causes the DQ pins to tri-state.
Crystal: Connections for 32.768 kHz crystal.
Capacitor supplied backup RTC supply voltage.
Battery supplied backup RTC supply voltage.
Power (+ 3V)
Hardware Store Busy (I/O)
Interrupt Output: Can be programmed to respond to the clock alarm,
the watchdog timer and the power monitor. Programmable to either
active high (push/pull) or active low (open-drain).
Autostore Capacitor: Supplies power to nvSRAM during power loss to
store data from SRAM to nonvolatile elements.
Ground
V
CAP
V
SS
Power Supply
Power Supply
February 2004
2
Document Control # ML0023 rev 0.3
STK17TA8
ABSOLUTE MAXIMUM RATINGS
a
Power Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . .–0.5V to +3.9V
Voltage on Input Relative to V
SS
. . . . . . . . . . –0.5V to (V
CC
+ 0.5V)
Voltage on DQ
0-7
. . . . . . . . . . . . . . . . . . . . . . –0.5V to (V
CC
+ 0.5V)
Temperature under Bias . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W
DC Output Current (1 output at a time, 1s duration) . . . . . . . . 15mA
Note a: Stresses greater than those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at con-
ditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rat-
ing conditions for extended periods may affect reliability.
DC CHARACTERISTICS(V
CC
= 3.0V
+20%,
-10%)
e
SYMBOL
I
CC b
1
PARAMETER
Average V
CC
Current
COMMERCIAL
MIN
MAX
70
60
55
1
5
0.5
0.3
±1
±1
200
1.6
2.0
V
SS
– .5
2.4
0.4
0
70
V
CC
+ .3
0.8
INDUSTRIAL
MIN
MAX
75
65
60
1
5
0.5
0.3
±1
±1
300
1.6
2.0
V
SS
– .5
2.4
0.4
– 40
85
V
CC
+ .3
0.8
UNITS
mA
mA
mA
mA
mA
mA
mA
µA
µA
nA
V
V
V
V
V
°C
All Inputs
All Inputs
I
OUT
= – 2mA
I
OUT
= 4mA
t
AVAV
= 25ns
t
AVAV
= 35ns
t
AVAV
= 45ns
NOTES
I
CC c
2
3
Average V
CC
Current during
STORE
Average V
CC
Current at t
AVAV
= 200ns
3V, 25°C, Typical
Average V
CAP
Current during
AutoStore™
Cycle
V
CC
Standby Current
(Standby, Stable CMOS Input Levels)
Input Leakage Current
Off-State Output Leakage Current
RTC Backup Current
RTC Backup Voltage
Input Logic “1” Voltage
Input Logic “0” Voltage
Output Logic “1” Voltage
Output Logic “0” Voltage
Operating Temperature
All Inputs Don’t Care, V
CC
= max
W
≥
(V
CC
– 0.2V)
All Others Cycling, CMOS Levels
All Inputs Don’t Care
E
≥
(V
CC
– 0.2V)
All Others V
IN
≤
0.2V or
≥
(V
CC
– 0.2V)
V
CC
= max
V
IN
= V
SS
to V
CC
V
CC
= max
V
IN
= V
SS
to V
CC
, E or G
≥
V
IH
I
CC b
I
CC c
4
I
SBd
I
ILK
I
OLK
I
BAK
V
BAK
V
IH
V
IL
V
OH
V
OL
T
A
Note b:
Note c:
Note d:
Note e:
I
CC
and I
CC
are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
1
3
I
CC
and I
CC
are the average currents required for the duration of the respective
STORE
cycles (t
STORE
) .
2
4
E
≥
V
IH
will not produce standby current levels until any nonvolatile cycle in progress has timed out.
V
CC
reference levels throughout this datasheet refer to V
CCX
.
3.0V
AC TEST CONDITIONS
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 3V
Input Rise and Fall Times
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤
5ns
Input and Output Timing Reference Levels . . . . . . . . . . . . . . . 1.5V
Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1
577 Ohms
OUTPUT
789 Ohms
30 pF
INCLUDING
SCOPE AND
FIXTURE
CAPACITANCE
f
SYMBOL
C
IN
C
OUT
PARAMETER
Input Capacitance
Output Capacitance
(T
A
= 25°C, f = 1.0MHz)
MAX
5
7
UNITS
pF
pF
CONDITIONS
∆V
= 0 to 3V
∆V
= 0 to 3V
Figure 1: AC Output Loading
Note f:
These parameters are guaranteed but not tested.
February 2004
3
Document Control # ML0023 rev 0.3
STK17TA8
SRAM READ CYCLES #1 & #2
NO.
1
2
3
4
5
6
7
8
9
10
11
SYMBOLS
#1, #2
t
ELQV
t
AVAV
g
(V
CC
= 3.0V +20%, -10%)
e
PARAMETER
STK17TA8-25
MIN
MAX
25
25
25
10
3
3
10
0
10
0
25
0
35
0
13
0
45
3
3
13
0
15
35
35
15
3
3
15
STK17TA8-35
MIN
MAX
35
45
45
20
STK17TA8-45
MIN
MAX
45
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Alt.
t
ACS
t
RC
t
AA
t
OE
t
OH
t
LZ
t
HZ
t
OLZ
Chip Enable Access Time
Read Cycle Time
Address Access Time
Output Enable to Data Valid
Output Hold after Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
t
AVQVh
t
GLQV
t
AXQXh
t
ELQX
t
EHQZi
t
GLQX
t
GHQZ
i
f
t
OHZ
t
PA
t
PS
t
ELICCH
t
EHICCLf
Note g: W must be high during SRAM READ cycles.
Note h: Device is continuously selected with E and G both low.
Note i: Measured
±
200mV from steady state output voltage.
SRAM READ CYCLE #1:
Address Controlled
g, h
2
t
AVAV
ADDRESS
5
3
t
AVQV
DATA VALID
t
AXQX
DQ (DATA OUT)
SRAM READ CYCLE #2:
E Controlled
g
2
t
AVAV
ADDRESS
6
t
ELQX
1
t
ELQV
1
1
t
EHICCL
7
t
EHQZ
E
G
8
t
GLQX
DQ (DATA OUT)
t
ELICCH
ACTIVE
t
GLQV
4
9
t
GHQZ
DATA VALID
10
I
CC
STANDBY
February 2004
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Document Control # ML0023 rev 0.3
STK17TA8
SRAM WRITE CYCLES #1 & #2
NO.
12
13
14
15
16
17
18
19
20
21
SYMBOLS
#1
t
AVAV
t
WLWH
t
ELWH
t
DVWH
t
WHDX
t
AVWH
t
AVWL
t
WHAX
t
WLQZ i, j
t
WHQX
#2
t
AVAV
t
WLEH
t
ELEH
t
DVEH
t
EHDX
t
AVEH
t
AVEL
t
EHAX
Alt.
t
WC
t
WP
t
CW
t
DW
t
DH
t
AW
t
AS
t
WR
t
WZ
t
OW
Write Cycle Time
Write Pulse Width
Chip Enable to End of Write
Data Set-up to End of Write
Data Hold after End of Write
Address Set-up to End of Write
Address Set-up to Start of Write
Address Hold after End of Write
Write Enable to Output Disable
Output Active after End of Write
3
PARAMETER
MIN
25
20
20
10
0
20
0
0
10
3
(V
CC
= 3.0V
+20%,
-10%)
e
STK17TA8-25
MAX
STK17TA8-35
MIN
35
25
25
12
0
25
0
0
13
3
MAX
STK17TA8-45
MIN
45
30
30
15
0
30
0
0
15
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note j: If W is low when E goes low, the outputs remain in the high-impedance state.
Note k: E or W must be
≥
V
IH
during address transitions.
Note l: HSB must be high during SRAM write cycles.
SRAM WRITE CYCLE #1:
W Controlled
k, l
12
t
AVAV
ADDRESS
14
t
ELWH
E
17
t
AVWH
13
t
WLWH
15
t
DVWH
DATA IN
t
WLQZ
DATA OUT
PREVIOUS DATA
HIGH IMPEDANCE
DATA VALID
19
t
WHAX
18
t
AVWL
W
16
t
WHDX
20
21
t
WHQX
SRAM WRITE CYCLE #2:
E Controlled
k, l
12
t
AVAV
ADDRESS
18
t
AVEL
E
14
t
ELEH
19
t
EHAX
17
t
AVEH
W
13
t
WLEH
15
t
DVEH
16
t
EHDX
DATA VALID
HIGH IMPEDANCE
DATA IN
DATA OUT
February 2004
5
Document Control # ML0023 rev 0.3
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