Field Programmable Gate Array, 96 CLBs, 1000 Gates, 258MHz, 96-Cell, CMOS, PQCC68, PLASTIC, LCC-68
| Parameter Name | Attribute value |
| Is it Rohs certified? | incompatible |
| Maker | Cypress Semiconductor |
| Parts packaging code | LCC |
| package instruction | PLASTIC, LCC-68 |
| Contacts | 68 |
| Reach Compliance Code | not_compliant |
| Other features | MAX. 56 I/OS; OTP BASED |
| maximum clock frequency | 258 MHz |
| Combined latency of CLB-Max | 6 ns |
| JESD-30 code | S-PQCC-J68 |
| JESD-609 code | e0 |
| length | 24.2316 mm |
| Configurable number of logic blocks | 96 |
| Equivalent number of gates | 1000 |
| Number of entries | 64 |
| Number of logical units | 96 |
| Output times | 56 |
| Number of terminals | 68 |
| Maximum operating temperature | 70 °C |
| Minimum operating temperature | |
| organize | 96 CLBS, 1000 GATES |
| Package body material | PLASTIC/EPOXY |
| encapsulated code | QCCJ |
| Encapsulate equivalent code | LDCC68,1.0SQ |
| Package shape | SQUARE |
| Package form | CHIP CARRIER |
| Peak Reflow Temperature (Celsius) | NOT SPECIFIED |
| power supply | 5 V |
| Programmable logic type | FIELD PROGRAMMABLE GATE ARRAY |
| Certification status | Not Qualified |
| Maximum seat height | 5.08 mm |
| Maximum supply voltage | 5.25 V |
| Minimum supply voltage | 4.75 V |
| Nominal supply voltage | 5 V |
| surface mount | YES |
| technology | CMOS |
| Temperature level | COMMERCIAL |
| Terminal surface | Tin/Lead (Sn/Pb) |
| Terminal form | J BEND |
| Terminal pitch | 1.27 mm |
| Terminal location | QUAD |
| Maximum time at peak reflow temperature | NOT SPECIFIED |
| width | 24.2316 mm |
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