V58C2256804SCLF5B datasheet, PDF

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V58C2256804SCLF5B: DescriptionDDR DRAM, 32MX8, 0.65ns, CMOS, PBGA60, ROHS COMPLIANT, MO-233, FBGA-60; Categorystorage storage; File Size920KB，61 Pages; ManufacturerProMOS Technologies Inc; Environmental Compliance

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V58C2256804SCLF5B Overview

DDR DRAM, 32MX8, 0.65ns, CMOS, PBGA60, ROHS COMPLIANT, MO-233, FBGA-60

V58C2256804SCLF5B Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	ProMOS Technologies Inc
Parts packaging code	BGA
package instruction	TBGA, BGA60,9X12,40/32
Contacts	60
Reach Compliance Code	compliant
ECCN code	EAR99
access mode	FOUR BANK PAGE BURST
Maximum access time	0.65 ns
Other features	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	200 MHz
I/O type	COMMON
interleaved burst length	2,4,8
JESD-30 code	R-PBGA-B60
length	13 mm
memory density	268435456 bit
Memory IC Type	DDR DRAM
memory width	8
Number of functions	1
Number of ports	1
Number of terminals	60
word count	33554432 words
character code	32000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	32MX8
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	TBGA
Encapsulate equivalent code	BGA60,9X12,40/32
Package shape	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	2.6 V
Certification status	Not Qualified
refresh cycle	8192
Maximum seat height	1.2 mm
self refresh	YES
Continuous burst length	2,4,8
Maximum standby current	0.03 A
Maximum slew rate	0.4 mA
Maximum supply voltage (Vsup)	2.7 V
Minimum supply voltage (Vsup)	2.5 V
Nominal supply voltage (Vsup)	2.6 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	8 mm

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V58C2256(804/404/164)SC

HIGH PERFORMANCE 256 Mbit DDR SDRAM

4 BANKS X 8Mbit X 8 (804)

4 BANKS X 4Mbit X 16 (164)

4 BANKS X 16Mbit X 4 (404)

DDR440

Clock Cycle Time (t

CK2

)

Clock Cycle Time (t

CK2.5

)

Clock Cycle Time (t

CK3

)

System Frequency (f

CK max

)

5ns

4.5ns

220 MHz

DDR400

5ns

200 MHz

DDR400

7.5ns

5ns

200 MHz

DDR400

7.5ns

6ns

5ns

200 MHz

DDR333

7.5ns

6ns

166 MHz

DDR266

7.5ns

7ns

143 MHz

Features

■

High speed data transfer rates with system frequency

up to 220 MHz

■

Data Mask for Write Control

■

Four Banks controlled by BA0 & BA1

■

Programmable CAS Latency: 2, 2.5, 3

■

Programmable Wrap Sequence: Sequential

or Interleave

■

Programmable Burst Length:

2, 4, 8 for Sequential Type

2, 4, 8 for Interleave Type

■

Automatic and Controlled Precharge Command

■

Power Down Mode

■

Auto Refresh and Self Refresh

■

Refresh Interval: 8192 cycles/64 ms

■

Available in 66-pin 400 mil TSOP or 60 Ball FBGA

■

SSTL-2 Compatible I/Os

■

Double Data Rate (DDR)

■

Bidirectional Data Strobe (DQS) for input and output

data, active on both edges

■

On-Chip DLL aligns DQ and DQs transitions with CK

transitions

■

Differential clock inputs CK and CK

■

Power Supply 2.5V ± 0.2V

■

Power Supply 2.6V ± 0.1V for DDR400 & DDR440

■

tRAS lockout supported

■

Concurrent auto precharge option is supported

*Note: (-45) Supports PC3600 module with 2.5-3-3 timing

(-5D) Supports PC3200 module with 2-3-3 timing

(-5B) Supports PC3200 module with 2.5-3-3 timing

(-5) Supports PC3200 module with 3-3-3 timing

(-6) Supports PC2700 module with 2.5-3-3 timing

(-7) Supports PC2100 module with 2-2-2 timing

Description

The V58C2256(804/404/164)SC is a four bank DDR

DRAM organized as 4 banks x 8Mbit x 8 (804), 4 banks x

4Mbit x 16 (164), or 4 banks x 16Mbit x 4 (404). The

V58C2256(804/404/164)SC achieves high speed data

transfer rates by employing a chip architecture that

prefetches multiple bits and then synchronizes the output

data to a system clock.

All of the control, address, circuits are synchronized

with the positive edge of an externally supplied clock. I/O

transactions are occurring on both edges of DQS.

Operating the four memory banks in an interleaved

fashion allows random access operation to occur at a

higher rate than is possible with standard DRAMs. A se-

quential and gapless data rate is possible depending on

burst length, CAS latency and speed grade of the device.

Device Usage Chart

Operating

Temperature

Range

0°C to 70°C

Package Outline

JEDEC 66 TSOP II

60 FBGA

•

CK Cycle Time (ns)

-45

•

Power

-6

•

-5D

•

-5B

•

-5

•

-7

•

Std.

•

Temperature

Mark

Blank

V58C2256(804/404/164)SC Rev.2.4 May 2006

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