CY14E256L
256 Kbit (32K x 8) nvSRAM
Features
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Functional Description
The Cypress CY14E256L is a fast static RAM with a nonvolatile
element in each memory cell. The embedded nonvolatile
elements incorporate QuantumTrap technology producing the
world’s most reliable nonvolatile memory. The SRAM provides
unlimited read and write cycles, while independent, nonvolatile
data resides in the highly reliable QuantumTrap cell. Data
transfers from the SRAM to the nonvolatile elements (the
STORE operation) takes place automatically at power down. On
power up, data is restored to the SRAM (the RECALL operation)
from the nonvolatile memory. Both the STORE and RECALL
operations are also available under software control. A hardware
STORE is initiated with the HSB pin.
25 ns, 35 ns, and 45 ns Access Times
Pin Compatible with STK14C88
Hands Off Automatic STORE on Power Down with External
68 µF Capacitor
STORE to QuantumTrap Nonvolatile Elements is Initiated by
Software, Hardware, or AutoStore on Power Down
RECALL to SRAM Initiated by Software or Power Up
Unlimited READ, WRITE, and RECALL Cycles
1,000,000 STORE Cycles to QuantumTrap
100 Year Data Retention to QuantumTrap
Single 5V±10% Operation
Commercial and Industrial Temperature
32-Pin SOIC Package (RoHS Compliance)
CDIP (300 mil) Package
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Logic Block Diagram
A
5
A
6
A
7
A
8
A
9
A
11
A
12
A
13
A
14
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Quantum Trap
512 X 512
STORE
ew
V
CC
V
CAP
POWER
CONTROL
STORE/
RECALL
CONTROL
ROW DECODER
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STATIC RAM
ARRAY
512 X 512
RECALL
D
HSB
SOFTWARE
DETECT
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DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
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ec
A
13
-
A
0
COLUMN I/O
COLUMN DEC
INPUT BUFFERS
N
DQ
5
DQ
6
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A
0
A
1
A
2
A
3
A
4
A
10
DQ
7
OE
CE
WE
Cypress Semiconductor Corporation
Document Number: 001-06968 Rev. *H
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised November 26, 2009
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CY14E256L
Contents
Features .................................................................................1
Functional Description .........................................................1
Logic Block Diagram ............................................................1
Contents ................................................................................2
Pin Configurations ...............................................................3
Device Operation ..................................................................4
SRAM Read ...........................................................................4
SRAM Write ...........................................................................4
AutoStore Operation ............................................................4
AutoStore Inhibit mode ........................................................4
Hardware STORE (HSB) Operation .....................................5
Hardware RECALL (Power Up) ............................................5
Software STORE ...................................................................5
Software RECALL .................................................................5
Data Protection .....................................................................6
Noise Considerations ...........................................................6
Hardware Protect ..................................................................6
Low Average Active Power ..................................................6
Preventing Store ...................................................................6
Best Practices .......................................................................7
Maximum Ratings .................................................................8
Operating Range ...................................................................8
DC Electrical Characteristics ..............................................8
Data Retention and Endurance ...........................................9
Capacitance ..........................................................................9
Thermal Resistance ..............................................................9
AC Test Conditions ..............................................................9
SRAM Read Cycle .........................................................10
SRAM Write Cycle ..........................................................11
AutoStore or Power Up RECALL .......................................12
Software Controlled STORE/RECALL Cycle .....................13
Switching Waveforms .........................................................14
Part Numbering Nomenclature
(Commercial and Industrial) ...............................................15
Ordering Information ...........................................................15
Document History Page ......................................................18
Sales, Solutions, and Legal Information ...........................19
Worldwide Sales and Design Support ............................19
Products .........................................................................19
Document Number: 001-06968 Rev. *H
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CY14E256L
Pin Configurations
Figure 1. Pin Diagram: 32-Pin SOIC/DIP
Table 1. Pin Definitions
Pin Name
A
0
–A
14
DQ
0
-DQ
7
WE
CE
OE
V
SS
V
CC
HSB
W
E
G
Alt
I/O Type
Input
Input
Input
Input
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Input or Output
Bidirectional Data I/O Lines.
Used as input or output lines depending on operation.
R
V
CAP
Document Number: 001-06968 Rev. *H
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Ground
Power Supply
Power Supply Inputs to the Device.
Input or Output
Hardware Store Busy (HSB).
When LOW, this output indicates a Hardware Store is in progress.
When pulled low external to the chip, it initiates a nonvolatile STORE operation. A weak internal
pull up resistor keeps this pin high if not connected (connection optional).
Power Supply
AutoStore Capacitor.
Supplies power to nvSRAM during power loss to store data from SRAM
to nonvolatile elements.
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Write Enable Input, Active LOW.
When the chip is enabled and WE is LOW, data on the I/O
pins is written to the specific address location.
Chip Enable Input, Active LOW.
When LOW, selects the chip. When HIGH, deselects the chip.
Output Enable, Active LOW.
The active LOW OE input enables the data output buffers during
read cycles. Deasserting OE HIGH causes the I/O pins to tri-state.
Ground for the Device.
The device is connected to ground of the system.
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Address Inputs.
Used to select one of the 32,768 bytes of the nvSRAM.
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CY14E256L
Device Operation
The CY14E256L nvSRAM is made up of two functional compo-
nents paired in the same physical cell. These are an SRAM
memory cell and a nonvolatile QuantumTrap cell. The SRAM
memory cell operates as a standard fast static RAM. Data in the
SRAM is transferred to the nonvolatile cell (the STORE
operation) or from the nonvolatile cell to SRAM (the RECALL
operation). This unique architecture enables storage and recall
of all cells in parallel. During the STORE and RECALL opera-
tions, SRAM READ and WRITE operations are inhibited. The
CY14E256L supports unlimited reads and writes similar to a
typical SRAM. In addition, it provides unlimited RECALL opera-
tions from the nonvolatile cells and up to one million STORE
operations.
having a capacitor of between 68 uF and 220 uF (+ 20%) rated
at 6V should be provided. The voltage on the V
CAP
pin is driven
to 5V by a charge pump internal to the chip. A pull up is placed
on WE to hold it inactive during power up.
Figure 2. AutoStore Mode
SRAM Read
The CY14E256L performs a READ cycle whenever CE and OE
are LOW while WE and HSB are HIGH. The address specified
on pins A
0–14
determines the 32,768 data bytes accessed. When
the READ is initiated by an address transition, the outputs are
valid after a delay of t
AA
(READ cycle 1). If the READ is initiated
by CE or OE, the outputs are valid at t
ACE
or at t
DOE
, whichever
is later (READ cycle 2). The data outputs repeatedly respond to
address changes within the t
AA
access time without the need for
transitions on any control input pins, and remains valid until
another address change or until CE or OE is brought HIGH, or
WE or HSB is brought LOW.
SRAM Write
R
AutoStore Operation
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A WRITE cycle is performed whenever CE and WE are LOW and
HSB is HIGH. The address inputs must be stable prior to entering
the WRITE cycle and must remain stable until either CE or WE
goes HIGH at the end of the cycle. The data on the common I/O
pins DQ
0–7
are written into the memory if it has valid t
SD
, before
the end of a WE controlled WRITE or before the end of an CE
controlled WRITE. Keep OE HIGH during the entire WRITE cycle
to avoid data bus contention on common I/O lines. If OE is left
LOW, internal circuitry turns off the output buffers t
HZWE
after WE
goes LOW.
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The CY14E256L stores data to nvSRAM using one of three
storage operations:
1. Hardware store activated by HSB
2. Software store activated by an address sequence
3. AutoStore on device power down
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AutoStore operation is a unique feature of QuantumTrap
technology and is enabled by default on the CY14E256L.
During normal operation, the device draws current from V
CC
to
charge a capacitor connected to the V
CAP
pin. This stored
charge is used by the chip to perform a single STORE operation.
If the voltage on the V
CC
pin drops below V
SWITCH
, the part
automatically disconnects the V
CAP
pin from V
CC
. A STORE
operation is initiated with power provided by the V
CAP
capacitor.
Figure 2
shows the proper connection of the storage capacitor
(V
CAP
) for automatic store operation. A charge storage capacitor
Document Number: 001-06968 Rev. *H
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In system power mode, both V
CC
and V
CAP
are connected to the
+5V power supply without the 68
μF
capacitor. In this mode, the
AutoStore function of the CY14E256L operates on the stored
system charge as power goes down. The user must, however,
guarantee that V
CC
does not drop below 3.6V during the 10 ms
STORE cycle.
To reduce unnecessary nonvolatile stores, AutoStore and
Hardware Store operations are ignored, unless at least one
WRITE operation has taken place since the most recent STORE
or RECALL cycle. Software initiated STORE cycles are
performed regardless of whether a WRITE operation has taken
place. An optional pull up resistor is shown connected to HSB.
The HSB signal is monitored by the system to detect if an
AutoStore cycle is in progress.
If the power supply drops faster than 20 us/volt before Vcc
reaches V
SWITCH
, then a 2.2 ohm resistor should be connected
between V
CC
and the system supply to avoid momentary excess
of current between V
CC
and V
CAP
.
AutoStore Inhibit mode
If an automatic STORE on power loss is not required, then V
CC
is tied to ground and + 5V is applied to V
CAP
(Figure
3).
This is
the AutoStore Inhibit mode, where the AutoStore function is
disabled. If the CY14E256L is operated in this configuration,
references to V
CC
are changed to V
CAP
throughout this data
sheet. In this mode, STORE operations are triggered through
software control or the HSB pin. To enable or disable Autostore
using an I/O port pin see
“Preventing Store”
on page 6. It is not
permissible to change between these three options ”on the fly”.
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CY14E256L
Figure 3. AutoStore Inhibit Mode
If the CY14E256L is in a WRITE state at the end of power up
RECALL, the SRAM data is corrupted. To help avoid this
situation, a 10 Kohm resistor is connected either between WE
and system V
CC
or between CE and system V
CC
.
Software STORE
Data is transferred from the SRAM to the nonvolatile memory by
a software address sequence. The CY14E256L software
STORE cycle is initiated by executing sequential CE controlled
READ cycles from six specific address locations in exact order.
During the STORE cycle, an erase of the previous nonvolatile
data is first performed followed by a program of the nonvolatile
elements. When a STORE cycle is initiated, input and output are
disabled until the cycle is completed.
Because a sequence of READs from specific addresses is used
for STORE initiation, it is important that no other READ or WRITE
accesses intervene in the sequence. If they intervene, the
sequence is aborted and no STORE or RECALL takes place.
To initiate the software STORE cycle, the following READ
sequence is performed:
1. Read address 0x0E38, Valid READ
2. Read address 0x31C7, Valid READ
3. Read address 0x03E0, Valid READ
4. Read address 0x3C1F, Valid READ
5. Read address 0x303F, Valid READ
6. Read address 0x0FC0, Initiate STORE cycle
Hardware STORE (HSB) Operation
The CY14E256L provides the HSB pin for controlling and
acknowledging the STORE operations. The HSB pin is used to
request a hardware STORE cycle. When the HSB pin is driven
LOW, the CY14E256L conditionally initiates a STORE operation
after t
DELAY
. An actual STORE cycle only begins if a WRITE to
the SRAM takes place since the last STORE or RECALL cycle.
The HSB pin also acts as an open drain driver that is internally
driven LOW to indicate a busy condition, while the STORE
(initiated by any means) is in progress. Pull up this pin with an
external 10K ohm resistor to V
CAP
if HSB is used as a driver.
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During any STORE operation, regardless of how it is initiated,
the CY14E256L continues to drive the HSB pin LOW, releasing
it only when the STORE is complete. After completing the
STORE operation, the CY14E256L remains disabled until the
HSB pin returns HIGH.
If HSB is not used, it is left unconnected.
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SRAM READ and WRITE operations, that are in progress when
HSB is driven LOW by any means, are given time to complete
before the STORE operation is initiated. After HSB goes LOW,
the CY14E256L continues SRAM operations for t
DELAY
. During
t
DELAY
, multiple SRAM READ operations take place. If a WRITE
is in progress when HSB is pulled LOW, it allows a time, t
DELAY
to complete. However, any SRAM WRITE cycles requested after
HSB goes LOW are inhibited until HSB returns HIGH.
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Hardware RECALL (Power Up)
During power up or after any low power condition (V
CC
<
V
RESET
), an internal RECALL request is latched. When V
CC
once again exceeds the sense voltage of V
SWITCH
, a RECALL
cycle is automatically initiated and takes t
HRECALL
to complete.
Document Number: 001-06968 Rev. *H
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The software sequence is clocked with CE controlled READs.
When the sixth address in the sequence is entered, the STORE
cycle commences and the chip is disabled. It is important that
READ cycles and not WRITE cycles are used in the sequence.
It is not necessary that OE is LOW for a valid sequence. After the
t
STORE
cycle time is fulfilled, the SRAM is again activated for
READ and WRITE operation.
Software RECALL
Data is transferred from the nonvolatile memory to the SRAM by
a software address sequence. A software RECALL cycle is
initiated with a sequence of READ operations in a manner similar
to the software STORE initiation. To initiate the RECALL cycle,
the following sequence of CE controlled READ operations is
performed:
1. Read address 0x0E38, Valid READ
2. Read address 0x31C7, Valid READ
3. Read address 0x03E0, Valid READ
4. Read address 0x3C1F, Valid READ
5. Read address 0x303F, Valid READ
6. Read address 0x0C63, Initiate RECALL cycle
Internally, RECALL is a two step procedure. First, the SRAM data
is cleared, and then the nonvolatile information is transferred into
the SRAM cells. After the t
RECALL
cycle time, the SRAM is once
again ready for READ and WRITE operations. The RECALL
operation does not alter the data in the nonvolatile elements. The
nonvolatile data can be recalled an unlimited number of times.
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