M28F411
M28F421
4 Megabit (x 8, Block Erase) FLASH MEMORY
PRELIMINARY DATA
SMALL SIZE PLASTIC PACKAGE TSOP40
MEMORY ERASE in BLOCKS
– One 16K Byte Boot Block (top or bottom lo-
cation) with hardware write and erase pro-
tection
– Two 8K Byte Key Parameter Blocks
– One 96K Byte Main Block
– Three 128K Byte Main Blocks
5V
±
10% SUPPLY VOLTAGE
12V
±
5% PROGRAMMING VOLTAGE
100,000 PROGRAM/ERASE CYCLES
PROGRAM/ERASE CONTROLLER
AUTOMATIC STATIC MODE
LOW POWER CONSUMPTION
– 60µA Typical in Standby
– 0.2µA Typical in Deep Power Down
– 20/25mA Typical Operating Consumption
HIGH SPEED ACCESS TIME: 70ns
EXTENDED TEMPERATURE RANGES
DESCRIPTION
The M28F411 and M28F421 FLASH MEMORIES
are non-volatile memories that may be erased
electrically at the block level and programmed by
byte.
Table 1. Signal Names
A0-A18
DQ0-DQ7
E
G
W
RP
V
PP
V
CC
V
SS
Address Inputs
Data Input / Outputs
Chip Enable
Output Enable
Write Enable
Reset/Power Down/Boot Block Unlock
Program Supply
Supply Voltage
Ground
TSOP40 (N)
10 x 20mm
Figure 1. Logic Diagram
VCC
VPP
19
A0-A18
RP
W
E
G
M28F411
M28F421
8
DQ0-DQ7
VSS
AI01131C
October 1995
This is preliminary infor mationon a new product now in developmen t or undergoing evaluation. Details are subject to change without notice.
1/34
M28F411, M28F421
Table 2. Absolute Maximum Ratings
(1)
Symbol
T
A
Parameter
Ambient Operating Temperature
grade
grade
grade
grade
1
3
5
6
Value
0 to 70
–40 to 125
–20 to 85
–40 to 85
–50 to 125
–65 to 150
–0.6 to 7
–0.6 to 7
–0.6 to 13.5
–0.6 to 14
–0.6 to 13.5
Unit
°C
°C
°C
V
V
V
V
V
T
BIAS
T
STG
V
IO
(2, 3)
Temperature Under Bias
Storage Temperature
Input or Output Voltages
Supply Voltage
A9 Voltage
Program Supply Voltage, during Erase
or Programming
RP Voltage
V
CC
V
A9 (2)
V
PP
(2)
V
RP (2)
Notes:
1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings”
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the SGS-THOMSON SURE Program and other
relevant quality documents.
2. Minimum Voltage may undershoot to –2V during transition and for less than 20ns.
3. Maximum DC voltage on I/O is V
CC
+ 0.5V, overshoot to 7V allowed for less than 20ns.
Figure 2. TSOP Pin Connections
DEVICE OPERATION
(cont’d)
The interface is directly compatible with most mi-
croprocessors. TSOP40 (10 x 20mm) package is
used.
A16
A15
A14
A13
A12
A11
A9
A8
W
RP
VPP
DU
A18
A7
A6
A5
A4
A3
A2
A1
1
40
10
11
M28F411
M28F421
(Normal)
31
30
20
21
AI01134C
A17
VSS
NC
NC
A10
DQ7
DQ6
DQ5
DQ4
VCC
VCC
NC
DQ3
DQ2
DQ1
DQ0
G
VSS
E
A0
Organization
The M28F411 and M28F421 are organized as
512K x 8. Memory control is provided by Chip
Enable, Output Enable and Write Enable inputs. A
Reset/Power Down/Boot block unlock, tri-level in-
put, places the memory in deep power down, nor-
mal operation or enables programming and
erasure of the Boot block.
Blocks
Erasure of the memories is in blocks. There are 7
blocks in the memory address space, one Boot
Block of 16K Bytes, two ’Key Parameter Blocks’ of
8K Bytes, one ’Main Block’ of 96K Bytes, and three
’Main Blocks’ of 128K Bytes. The M28F411 mem-
ory has the Boot Block at the top of the memory
address space (7FFFFh) and the M28F421 locates
the Boot Block starting at the bottom (00000h).
Erasure of each block takes typically 1 second and
each block can be programmed and erased over
100,000 cycles.
The Boot Block is hardware protected from acci-
dental programming or erasure depending on the
RP signal. Program/Erase commands in the Boot
Block are executed only when RP is at 12V.
Block erasure may be suspended while data is read
from other blocks of the memory, then resumed.
Warning:
NC = Not Connected, DU = Don’t Use
2/34
M28F411, M28F421
Table 3. Operations
Operation
Read Byte
Write Byte
Output Disable
Standby
Power Down
E
V
IL
V
IL
V
IL
V
IH
X
G
V
IL
V
IH
V
IH
X
X
W
V
IH
V
IL
V
IH
X
X
RP
V
IH
V
IH
V
IH
V
IH
V
IL
DQ0 - DQ7
Data Output
Data Input
Hi-Z
Hi-Z
Hi-Z
Note:
X = V
IL
or V
IH
, V
PP
= V
PPL
or V
PPH
Table 4. Electronic Signature
Code
Manufact. Code
Device Code
M28F411
M28F421
Note:
RP = V
IH
Device
E
V
IL
V
IL
V
IL
G
V
IL
V
IL
V
IL
W
V
IH
V
IH
V
IH
A0
V
IL
V
IH
V
IH
A9
V
ID
V
ID
V
ID
A1-A8 & A10-A18
Don’t Care
Don’t Care
Don’t Care
DQ0 - DQ7
20h
0F6h
0FEh
Bus Operations
Six operations can be performed by the appropriate
bus cycles, Read Byte from the Array, Read Elec-
tronic Signature, Output Disable, Standby, Power
Down and Write the Command of an Instruction.
Command Interface
Commands can be written to a Command Interface
(C.I.) latch to perform read, programming, erasure
and to monitor the memory’s status. When power
is first applied, on exit from power down or if V
CC
falls below V
LKO
, the command interface is reset to
Read Memory Array.
Instructions and Commands
Eight Instructions are defined to perform Read
Memory Array, Read Status Register, Read Elec-
tronic Signature, Erase, Program, Clear Status
Register, Erase Suspend and Erase Resume. An
internalProgram/EraseController (P/E.C.) handles
all timing and verification of the Program and Erase
instructions and provides status bits to indicate its
operation and exit status. Instructions are com-
posed of a first command write operation followed
by either second command write, to confirm the
commands for programming or erase, or a read
operationto read data from the array, the Electronic
Signature or the Status Register.
For added data protection, the instructions for byte
program and block erase consist of two commands
that are written to the memory and which start the
automatic P/E.C. operation. Byte programming
takes typically 9µs, block erase typically 1 second.
Erasure of a memory block may be suspended in
order to read data from another block and then
resumed. A Status Register may be read at any
time, including during the programming or erase
cycles, to monitor the progress of the operation.
Power Saving
The M28F411 and M28F421 have a number of
power saving features. A CMOS standby mode is
entered when the Chip Enable E and the Re-
set/Power Down (RP) signals are at V
CC
, when the
supply current drops to typically 60µA. A deep
power down mode is enabled when the Re-
set/Power Down (RP) signal is at V
SS
, when the
supply current drops to typically 0.2µA. The time
required to awake from the deep power down mode
is 300ns maximum, with instructions to the C.I.
recognised after only 210ns.
DEVICE OPERATION
Signal Descriptions
A0-A18 Address Inputs.
The address signals,
inputs for the memory array, are latched during a
write operation.
A9 Address Input is also used for the Electronic
Signature Operation. When A9 is raised to 12V the
Electronic Signature may be read. The A0 signal is
used to read two bytes, when A0 is Low the Manu-
facturer code is read and when A0 is High the
Device code.
3/34
M28F411, M28F421
Table 5. Instructions
Mnemo
nic
Instruction
Read
Memory
Array
Read
Status
Register
Read
Electronic
Signature
Erase
Program
Clear
Status
Register
Erase
Suspend
Erase
Resume
Cycles
Operation
1+
Write
1st Cycle
Address
(1)
X
Data
0FFh
Operation
Read
(2)
2nd Cycle
Address
(1)
Read
Address
Data
Data
RD
RSR
1+
Write
X
70h
Read
(2)
X
Status
Register
RSIG
3
Write
X
90h
Read
(2)
Signature
(3)
Adress
Block
Address
Address
Signature
EE
PG
2
2
Write
Write
X
X
20h
40h or
10h
50h
Write
Write
0D0h
Data Input
CLRS
1
Write
X
ES
ER
1
1
Write
Write
X
X
0B0h
0D0h
Notes:
1. X = Don’t Care.
2. The first cycle of the RD, RSR or RSIG instruction is followed by read operations to read memory array, Status Register
or Electronic Signature codes. Any number of Read cycle can occur after one command cycle.
3. Signature address bit A0=V
IL
will output Manufacturer code. Address bit A0=V
IH
will output Device code. Other address bits are
ignored.
Table 6. Commands
Hex Code
00h
10h
20h
40h
50h
70h
90h
0B0h
0D0h
0FFh
Command
Invalid/Reserved
Alternative Program Set-up
Erase Set-up
Program Set-up
Clear Status Register
Read Status Register
Read Electronic Signature
Erase Suspend
Erase Resume/Erase Confirm
Read Array
DQ0-DQ7 Data Input/Outputs.
The data inputs, a
byte to be programmed or a command to the C.I.,
are latched when both Chip Enable E and Write
Enable W are active. The data output from the
memory Array, the Electronic Signature or Status
Register is valid when Chip Enable E and Output
Enable G are active. The output is high impedance
when the chip is deselected or the outputs are
disabled.
E Chip Enable.
The Chip Enable activates the
memory control logic, input buffers, decoders and
sense amplifiers. E High de-selects the memory
and reduces the power consumption to the standby
level. E can also be used to control writing to the
command register and to the memory array, while
W remains at a low level. Both addresses and data
inputs are then latched on the rising edge of E.
RP Reset/Power Down.
This is a tri-level input
which locks the Boot Block from programming and
erasure, and allows the memory to be put in deep
power down.
When RP is High (up to 6.5V maximum) the Boot
Block is locked and cannot be programmed or
erased. When RP is above 11.4V the Boot Block is
unlocked for programming or erasure.
With RP Low the memory is in deep power down,
and if RP is within V
SS
+0.2V the lowest supply
current is absorbed.
4/34
M28F411, M28F421
Table 7. Status Register
Mnemon
ic
Bit
Name
Logic
Level
’1’
P/ECS
7
P/E.C. Status
’0’
Erase
Suspend
Status
’1’
’0’
’1’
ES
5
Erase Status
’0’
’1’
’0’
’1’
VPPS
3
V
PP
Status
’0’
2
1
0
Reserved
Reserved
Reserved
V
PP
OK
Erase Success
Program Error
Program
Success
V
PP
Low, Abort
Busy
Suspended
In progress or
Completed
Erase Error
Definition
Ready
Note
Indicates the P/E.C. status, check during Program
or Erase, and on completion before checking bits
b4 or b5 for Program or Erase Success
On an Erase Suspend instruction P/ECS and
ESS bits are set to ’1’. ESS bit remains ’1’ until an
Erase Resume instruction is given.
ESS
6
ES bit is set to ’1’ if P/E.C. has applied the
maximum number of erase pulses to the block
without achieving an erase verify.
PS
4
Program
Status
PS bit set to ’1’ if the P/E.C. has failed to program
a byte.
VPPS bit is set if the V
PP
voltage is below
V
PPH
(min) when a Program or Erase instruction
has been executed.
Notes:
Logic level ’1’ is High, ’0’ is Low.
G Output Enable.
The Output Enable gates the
outputs through the data buffers during a read
operation.
W Write Enable.
It controls writing to the Com-
mand Register and Input Address and Data
latches. Both Addresses and Data Inputs are
latched on the rising edge of W.
V
PP
ProgramSupply Voltage.
This supply voltage
is used for memory Programming and Erase.
V
PP
±10%
tolerance option is provided for applica-
tion requiring maximum 100 write and erase cycles.
V
CC
Supply Voltage.
It is the main circuit supply.
V
SS
Ground.
It is the reference for all voltage
measurements.
Memory Blocks
The memory blocks of the M28F411 and M28F421
are shown in Figure 8. The difference between the
two productsis simply an inversion of the block map
to position the Boot Block at the top or bottom of
the memory. The selection of the Boot Block at the
top or bottom of the memory depends on the
microprocessor needs.
Each block of the memory can be erased sepa-
rately, but only by one block at a time. The erase
operation is managed by the P/E.C. but can be
suspended in order to read from another block and
then resumed.
Programming and erasure of the memory is dis-
abled when the program supply is at V
PPL
. For
successful programming and erasure the program
supply must be at V
PPH
.
The Boot Block provides additional hardware secu-
rity by use of the RP signal which must be at V
HH
before any program or erase operation will be
executed by the P/E.C. on the Boot Block.
5/34
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