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P4C164L-70L32M

Description
Standard SRAM, 8KX8, 70ns, CMOS, CQCC32, 0.450 X 0.550 INCH, CERAMIC, LCC-32
Categorystorage    storage   
File Size1MB,16 Pages
ManufacturerPyramid Semiconductor Corporation
Websitehttp://www.pyramidsemiconductor.com/
Download Datasheet Parametric View All

P4C164L-70L32M Overview

Standard SRAM, 8KX8, 70ns, CMOS, CQCC32, 0.450 X 0.550 INCH, CERAMIC, LCC-32

P4C164L-70L32M Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerPyramid Semiconductor Corporation
Parts packaging codeQFJ
package instruction0.450 X 0.550 INCH, CERAMIC, LCC-32
Contacts32
Reach Compliance Codecompliant
ECCN code3A001.A.2.C
Maximum access time70 ns
I/O typeCOMMON
JESD-30 codeR-CQCC-N32
JESD-609 codee0
length13.97 mm
memory density65536 bit
Memory IC TypeSTANDARD SRAM
memory width8
Number of functions1
Number of terminals32
word count8192 words
character code8000
Operating modeASYNCHRONOUS
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
organize8KX8
Output characteristics3-STATE
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeQCCN
Encapsulate equivalent codeLCC32,.45X.55
Package shapeRECTANGULAR
Package formCHIP CARRIER
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply5 V
Certification statusNot Qualified
Maximum seat height1.905 mm
Maximum standby current0.0002 A
Minimum standby current2 V
Maximum slew rate0.145 mA
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelMILITARY
Terminal surfaceTIN LEAD
Terminal formNO LEAD
Terminal pitch1.27 mm
Terminal locationQUAD
Maximum time at peak reflow temperatureNOT SPECIFIED
width11.43 mm
P4C164
ULTRA HIGH SPEED 8K X 8
STATIC CMOS RAMS
FEATURES
Full CMOS, 6T Cell
High Speed (Equal Access and Cycle Times)
– 8/10/12/15/20/25/35/70/100 ns (Commercial)
– 10/12/15/20/25/35/70/100 ns(Industrial)
– 12/15/20/25/35/45/70/100 ns (Military)
Low Power Operation
Output Enable and Dual Chip Enable Control
Functions
Single 5V±10% Power Supply
Data Retention with 2.0V Supply, 10 µA Typical
Current (P4C164L Only)
Common Data I/O
Fully TTL Compatible Inputs and Outputs
Standard Pinout (JEDEC Approved)
– 28-Pin 300 mil Plastic DIP, SOJ
– 28-Pin 600 mil Plastic DIP
– 28-Pin 300 mil SOP (70 & 100ns)
– 28-Pin 300 mil Ceramic DIP
– 28-Pin 600 mil Ceramic DIP
– 28-Pin 350 x 550 mil LCC
– 32-Pin 450 x 550 mil LCC
– 28-Pin Glass-sealed CERPACK
– 28-Pin Solder-sealed CERPACK
DESCRIPTIOn
The P4C164 is a 65,536-bit ultra high-speed static RAM
organized as 8K x 8. The CMOS memory requires no
clocks or refreshing and has equal access and cycle times.
Inputs are fully TTL-compatible. The RAM operates from
a single 5V±10% tolerance power supply. With battery
backup (P4C164L Only), data integrity is maintained with
supply voltages down to 2.0V. Current drain is typically 10
µA from a 2.0V supply.
Access times as fast as 8 nanoseconds are available,
permitting greatly enhanced system operating speeds.
The P4C164 is available in 28-pin 300 mil DIP and SOJ,
28-pin 600 mil plastic and ceramic DIP, 28-pin 350 x 550 mil
LCC, 32-pin 450 x 550 mil LCC, and 28-pin glass-sealed
CERPACK and solder-sealed flatpack.
FUnCTIOnAL BLOCK DIAGRAM
PIn COnFIGURATIOnS
DIP (P5, P6, C5, C5-1, D5-1, D5-2),
SOJ (J5), CERPACK (F4), SOLDER-SEAL FLATPACK (FS-5), SOP (S6)
SEE PAGE 8 FOR LCC PIN CONFIGURATIONS
Document #
SRAM115
REV H
Revised April 2011
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