DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD75237
4-BIT SINGLE-CHIP MICROCOMPUTER
DESCRIPTION
The
µ
PD75237 is a microcomputer with a CPU capable of 1-, 4-, and 8-bit-wise data processing, a ROM, a RAM,
I/O ports, a fluorescent display tube (FIP
®
) controller/driver, A/D converters, a watch timer, a timer/pulse generator
capable of outputting 14-bit PWM, a serial interface and a vectored interrupt function integrated on a single-chip.
The
µ
PD75237 has the more improved peripheral functions including the RAM capacity, FIP controller/driver
display capabilities, I/O ports, A/D converter and serial interface than those of the
µ
PD75217.
The
µ
PD75237 is most suited for advanced and popular VCR timer and tuner applications, single-chip configu-
rations of system computers, advanced CD players and advanced microwave ovens.
The
µ
PD75P238 PROM product and various types of development tools (IE-75001-R, assemblers and others) are
available for evaluation in system development or small-volume production.
FEATURES
q
Built-in, large-capacity ROM and RAM
• Program memory (ROM): 24K
×
8
• Data memory (RAM): 1K
×
4
I/O port: 64 ports (except FIP dedicated pins)
Minimum instruction execution time: 0.67
µ
s (when
operated at 6.0 MHz)
Instruction execution time varying function to achieve
a wide range of power supply voltages
Built-in programmable FIP controller/driver
• Number of segments: 9 to 24
• Number of digits: 9 to 16
q
q
q
q
8-bit A/D converter: 8 channels
Powerful timer/counter function: 5 channels
8-bit serial interface: 2 channels
Interrupt function with importance attached to appli-
cations
Product with built-in PROM:
µ
PD75P238
q
q
q
q
q
ORDERING INFORMATION
Ordering Code
Package
94-pin plastic QFP (20
×
20 mm)
Quality Grade
Standard
µ
PD75237GJ-×××-5BG
Please refer to “Quality grade on NEC Semiconductor Devices” (Document number IEI-1209) published by
NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
The information in this document is subject to change without notice.
Document No. IC-2807A
(O. D. No. IC-8009A)
Date Published March 1993 P
Printed in Japan
The mark
5
shows major revised points.
© NEC Corporation 1991
µ
PD75237
LIST OF
µ
PD75237 FUNCTIONS
Item
Built-in memory capacity
ROM:
24448
×
8 bits, RAM:
Function
1024
×
4bits
I/O line
except FIP
dedicated pins
q
(
)
64 lines
q
q
Input pin
: 16
Input/output pin : 24
Output pin
: 24
q
Instruction cycle
q
q
q
0.67
µ
s/1.33
µ
s/2.67
µ
s/10.7
µ
s (when operated at 6.0 MHz)
0.95
µ
s/1.91
µ
s/3.82
µ
s/15.3
µ
s (when operated at 4.19 MHz)
122
µ
s (when operated at 32.768 kHz)
Number of segments : 9 to 24
Number of digits
: 9 to 16
Dimmer function
: 8 levels
Pull-down resistor mask option
Key scan interrupt generation enabled
q
q
Fluorescent display
tube (FIP)
controller/driver
q
q
q
q
Timer/counter
5 channels
q
q
q
Basic interval timer
: Watchdog timer applicable
Timer/event counter
Watch timer
: Buzzer output enabled
Timer/pulse generator : 14-bit PWM output enabled
Event counter
SBI/3-wire type
3-wire type
Serial interface
2 channels
q
q
q
Multi-interrupt enabled by hardware
q
q
External interrupt:
3 interrupts
q
q
q
External test input:
1 input
q
q
q
Interrupt
q
Internal interrupt:
5 interrupts
q
q
q
q
Internal test input:
2 inputs
q
q
Both-edge detection
Detected edge programmable (with noise
remove function)
Detected edge programmable
Rising edge detection
Timer/pulse generator
Timer/event counter
Basic interval timer
Serial interface #0
Key scan interrupt
Clock timer
Serial interface #1
System clock oscillator
q
q
Main system clock
Subsystem clock
: 6.0 MHz, 4.19 MHz
: 32.768 kHz standard
: Pull-down resistor or open-drain output
: Pull-up resistors
: Pull-down resistor
q
Mask option
q
q
High withstand voltage port
Ports 4 and 5
Port 7
Operating temperature
range
Operating voltage
Package
–40 to +85
°C
2.7 to 6.0 V (standby data hold: 2.0 to 6.0 V)
94-pin plastic QFP (20
×
20 mm)
2
µ
PD75237
PIN CONFIGURATION
AN1
AN2
AN3
AN4/P90
AN5/P91
AN6/P92
AN7/P93
AV
SS
RESET
P00/INT4
P01/SCK0
P02/SO0/SB0
P03/SI0/SB1
P10/INT0
P11/INT1
P12/INT2
P13/TI0
P20/PTO0
P21
P22/PCL
P23/BUZ
P30
P31
AN0
AV
REF
AV
DD
V
DD
V
DD
X2
X1
IC
XT2
XT1
V
SS
S16/P100
S17/P101
S18/P102
S19/P103
S20/P110
S21/P111
S22/P112
S23/P113
S0/P120
S1/P121
S2/P122
S3/P123
94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 7372
71
1
70
2
69
3
68
4
67
5
66
6
65
7
64
8
63
9
62
10
61
11
60
12
59
13
58
14
57
15
56
16
55
17
54
18
53
19
52
20
51
21
50
22
49
23
48
24
2526272829303132333435363738
39404142434445
4647
P32
P33
P40
P41
P42
P43
V
SS
P50
P51
P52
P53
P60
P61
P62
P63
P70
P71
P72
P73
P80/PPO
P81/SCK1
P82/SO1
P83/SI1
V
DD
Note
Be sure to supply power to AV
DD
, V
DD
, V
SS
and AV
SS
pins (pin Nos. 3, 4, 5, 11, 30, 48, 65 and 87) .
Connect the IC (Internally Connected) pin to GND.
Remarks
S4/P130
S5/P131
S6/P132
S7/P133
S8/P140
S9/P141
V
DD
V
LOAD
T15/S10/P142
T14/S11/P143
PH0/T13/S12/P150
PH1/T12/S13/P151
PH2/T11/S14/P152
PH3/T10/S15/P153
T9
T8
T7
T6
T5
T4
T3
T2
T1
T0
µ
PD75237GJ-×××-5BG
3
4
PORT0
P00-P03
P10-P13
P20-P23
P30-P33
P40-P43*
P50-P53*
P60-P63
P70-P73
4
4
PORT9
10
4
FIP
CONTROLLER/
DRIVER
fx/2
CLOCK
GENERATOR
SUB
MAIN
STAND BY
CONTROL
N
BASIC
INTERVAL
TIMER
4
4
4
4
4
4
4
4
PORT1
PROGRAM
COUNTER (15)
ALU
SBS (2)
PORT3
PORT4
PORT5
PORT6
PORT7
ROM
PROGRAM
MEMORY
24448x8
PORT8
RAM
DATA MEMORY
1024x4
DECODE
AND
CONTROL
CY
PORT2
SP (8)
TI0
INTBT
BLOCK DIAGRAM
TI0/P13
PTO0/P20
TIMER/EVENT
COUNTER
#0
INTT0
BANK
BUZ/P23
WATCH
TIMER
INTW
GENERAL REG.
PPO/P80
TIMER/PULSE
GENERATOR
INTTPG
P80-P83
P90-P93
T0-T9
SI0/SB1/P03
SO0/SB0/P02
SCK0/P01
SERIAL
INTERFACE0
INTCSI
SI1/P83
SO1/P82
SCK1/P81
SERIAL
INTERFACE1
2
10
8
T10/S15/PH3/P153-
T13/S12/PH0/P150
T14/S11/P143-
T15/S10/P142
S0/P120-S9/P141
S16/P100-S23/P113
INT0/P10
INT1/P11
INT2/P12
INT4/P00
CLOCK
DIVIDER
INTERRUPT
CONTROL
CLOCK
OUTPUT
CONTROL
CPU CLOCK
Φ
PORT10-15 24
V
LOAD
P100-P153
TI0
PCL/P22
XT1XT2 X1 X2
RESET
V
DD
V
SS
V
DD
EVENT
COUNTER
8
AN0-AN3
AN4/P90-AN7/P93
AV
DD
AV
REF
AV
SS
A/D
CONVERTER
µ
PD75237
BIT SEQ.
BUFFER(16)
*
PORT4 and PORT5 are 10 V middle-high voltage N-ch open-drain input/output ports.
µ
PD75237
CONTENTS
1.
PIN FUNCTIONS ......................................................................................................................................... 7
1.1
1.2
1.3
1.4
PORT PINS ........................................................................................................................................................... 7
NON-PORT PINS .................................................................................................................................................. 9
PIN INPUT/OUPUT CIRCUIT LIST ................................................................................................................... 11
RECOMMENDED CONNECTIONS OF
µ
PD75237 UNUSED PINS ............................................................... 15
2.
µ
PD75237 ARCHITECTURE AND MEMORY MAP................................................................................ 16
2.1
2.2
2.3
DATA MEMORY BANK CONFIGURATION AND ADDRESSING MODE ..................................................... 16
GENERAL REGISTER BANK CONFIGURATION ............................................................................................ 19
MEMORY MAPPED I/O .................................................................................................................................... 22
3.
INTERNAL CPU FUNCTIONS .................................................................................................................. 28
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
PROGRAM COUNTER (PC): 15 BITS ..............................................................................................................
PROGRAM MEMORY (ROM): 24448 WORDS
×
8 BITS ...............................................................................
DATA MEMORY ................................................................................................................................................
GENERAL REGISTER: 8
×
4 BITS
×
4 BANKS ...............................................................................................
ACCUMULATOR ...............................................................................................................................................
STACK POINTER (SP) AND STACK BANK SELECT REGISTER (SBS) .......................................................
PROGRAM STATUS WORD (PSW): 8 BITS ...................................................................................................
BANK SELECT REGISTER (BS) .......................................................................................................................
28
28
30
32
33
33
36
40
4.
PERIPHERAL HARDWARE FUNCTIONS ............................................................................................... 41
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
4.10
4.11
4.12
DIGITAL INPUT/OUTPUT PORTS ................................................................................................................... 41
CLOCK GENERATOR ........................................................................................................................................ 50
CLOCK OUTPUT CIRCUIT ................................................................................................................................ 58
BASIC INTERVAL TIMER ................................................................................................................................. 61
TIMER/EVENT COUNTER ................................................................................................................................ 63
WATCH TIMER .................................................................................................................................................. 69
TIMER/PULSE GENERATOR ........................................................................................................................... 71
EVENT COUNTER ............................................................................................................................................. 77
SERIAL INTERFACE .......................................................................................................................................... 79
A/D CONVERTER ........................................................................................................................................... 113
BIT SEQUENTIAL BUFFER: 16 BITS ............................................................................................................. 119
FIP CONTROLLER/DRIVER ............................................................................................................................ 119
5.
INTERRUPT FUNCTIONS ...................................................................................................................... 131
5.1
5.2
5.3
5.4
5.5
INTERRUPT CONTROL CIRCUIT CONFIGURATION ...................................................................................
INTERRUPT CONTROL CIRCUIT HARDWARE DEVICES ...........................................................................
INTERRUPT SEQUENCE ................................................................................................................................
MULTI-INTERRUPT SERVICE CONTROL .....................................................................................................
VECTOR ADDRESS SHARING INTERRUPT SERVICING ...........................................................................
131
133
138
139
141
6.
STANDBY FUNCTIONS ......................................................................................................................... 142
6.1
6.2
6.3
STANDBY MODE SETTING AND OPERATING STATE .............................................................................. 142
STANDBY MODE RELEASE .......................................................................................................................... 144
OPERATION AFTER STANDBY MODE RELEASE ....................................................................................... 146
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