VSC7185TW datasheet, PDF - EEWORLD Datasheet

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VSC7185TW: DescriptionEthernet Transceiver, PBGA208, 23 MM, TBGA-208; CategoryWireless rf/communication Telecom circuit; File Size240KB，18 Pages; ManufacturerVitesse Semiconductor Corporation; Websitehttp://www.vitesse.com/

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VSC7185TW Overview

Ethernet Transceiver, PBGA208, 23 MM, TBGA-208

VSC7185TW Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Vitesse Semiconductor Corporation
Parts packaging code	BGA
package instruction	BGA, BGA208,17X17,50
Contacts	208
Reach Compliance Code	compliant
JESD-30 code	S-PBGA-B208
JESD-609 code	e0
length	23 mm
Humidity sensitivity level	3
Number of functions	1
Number of terminals	208
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA208,17X17,50
Package shape	SQUARE
Package form	GRID ARRAY
Peak Reflow Temperature (Celsius)	225
power supply	3.3 V
Certification status	Not Qualified
Maximum slew rate	0.77 mA
Nominal supply voltage	3.3 V
surface mount	YES
Telecom integrated circuit types	ETHERNET TRANSCEIVER
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	30
width	23 mm

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VITESSE

SEMICONDUCTOR CORPORATION

Preliminary Data Sheet

VSC7185

Features

• Four Complete Transceiver Functions in a Single

Integrated Circuit

• SSTL-2 Compatible Parallel Data and Clocks

• 1.05Gb/s to 1.36Gb/s Operation per Channel

• Common Transmit Byte Clock

• TTL or PECL Reference Clock Input

• Per-Channel 1/10

Baud Rate Recovered Clocks

and Comma Detect Outputs

Quad Transceiver for

Gigabit Ethernet and Fibre Channel

• Common Comma Detect Enable Input

• Common Serial / Parallel Loopback Controls

• Cable Equalization in Receivers

• JTAG Access Port

• 3.3V Power Supply, 2.5W Dissipation

• 208 pin, 23mm BGA Package

General Description

The VSC7185 is a full-speed quad Gigabit Ethernet and Fibre Channel Transceiver IC. 8B/10B encoded (or

equivalent scheme) transmit characters are serialized onto high-speed differential outputs (SOi+/-) at speeds up

to 1.36Gb/s. Each of the four transmitters has a 5-bit wide parallel input bus. Parallel data is latched in by an

internal clock running at up to 272MHz (2x the rate of the external common Transmit Byte Clock). Transmit

data must be presented synchronously with the common transmit byte clock. Each receiver samples the serial

receive data (SIi+/-), recovers the clock and data, deserializes it into 5-bit receive half-characters, outputs a

recovered 2x or 1x clock and detects “Comma” characters. The VSC7185 contains on-chip PLL circuitry for

synthesis of the baud-rate transmit clock and extraction of the clocks from the received serial streams.

VSC7185 Block Diagram (1 of 4 Channels)

RXi(0:4)

Serial to

Q Parallel D

÷5

SIi+

SIi-

RCi1

RCi0

RSYN

SYNi

SYNC

PLUP

SLPN

Clock

Recovery

÷10

Unit

Comma

Detect

Loopback

Control

TXi(0:4)

RFCT

RFC+

RFC-

RFCM

CAP0

CAP1

Parallel

to Serial

SOi+

SOi-

x10/x20

RFCO

Clock

Multiply

Unit

G52324-0, Rev. 3.0

8/28/00

VITESSE

SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

Page 1

VITESSE

SEMICONDUCTOR CORPORATION

Quad Transceiver for

Gigabit Ethernet and Fibre Channel

Preliminary Data Sheet

VSC7185

Functional Description

Notation

In this document, each of the four channels are identified as Channel 0, 1, 2 or 3. When discussing a signal

on any specific channel, the signal will have the channel number embedded in the name, for example,

“TX3(0:4).” When referring to the common behavior of a signal which is used on each of the four channels, the

notation “i” is used. Differential signals, i.e. SOi+ and SOi-, may be referred to as a single signal, i.e. SOi, by

dropping reference to the “+” and “-”. RFC refers to the active reference clock input(s), RFCT or RFC+/RFC-.

Clock Synthesizer

To achieve a baud rate clock between 1.05GHz and 1.36GHz, the VSC7185 Clock Multiplier Unit (CMU)

multiplies the reference frequency provided on the RFC input by 10 when RFCM=1, or by 20 when RFCM=0.

The RFCT input is TTL, and the REF+/- inputs are PECL. The on-chip PLL uses a single external 0.1

F capac-

itor, connected between CAP0 and CAP1, to control the Loop Filter. This capacitor should be a multilayer

ceramic dielectric, or better, with at least a 5V working voltage rating and a good temperature coefficient. NPO

is preferred but X7R may be acceptable. These capacitors are used to minimize the impact of common-mode

noise on the Clock Multiplier Unit, especially power supply noise. Higher value capacitors provide better

robustness in systems. NPO is preferred because if an X7R capacitor is used, the power supply noise sensitivity

will vary with temperature.

For best noise immunity, the designer may use a three capacitor circuit with one differential capacitor

between CAP0 and CAP1, C1, a capacitor from CAP0 to ground, C2, and a capacitor from CAP1 to ground, C3

(see Figure 1). Larger values are better but 0.1

F is adequate. However, if the designer cannot use a three

capacitor circuit, a single differential capacitor, C1, is adequate. These components should be isolated from

noisy traces.

Figure 1: Loop Filter Capacitors (Best Circuit)

CAP0

VSC7185

CAP1

C1=C2=C3= >0.1uF

MultiLayer Ceramic

Surface Mount

NPO (Preferred) or X7R

5V Working Voltage Rating

Serializer

The VSC7185 accepts 5-bit parallel SSTL-2 input data on the four TXi(0:4) buses along with an SSTL-2

byte clock (TC) and serializes them into four high-speed serial streams. At the source, TXi(0:4) and TC switch

synchronously with respect to an internal 5 bit-time clock. TC and RFC must be derived from the same fre-

quency source so that TC and RFC have a fixed but arbitrary phase relationship when system clocks are stable.

The 5-bit parallel transmission half-characters will be serialized and transmitted on the SOi+/- PECL differen-

tial outputs at the baud rate, with bit TXi0 (10B bit “a” or “i”) transmitted first. User data should be encoded

using 8B/10B or an equivalent code.

Page 2

VITESSE

SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

G52324-0, Rev. 3.0

8/28/00

VITESSE

SEMICONDUCTOR CORPORATION

Preliminary Data Sheet

VSC7185

Quad Transceiver for

Gigabit Ethernet and Fibre Channel

Clock Recovery

The VSC7185 accepts differential high-speed serial input from the selected source (either the PECL SIi+/

SIi- pins or the internal SOi+/- data), extracts the clock and retimes the data. Equalizers are included in the

receiver to open the data eye and compensate for InterSymbol Interference (ISI) which may be present in the

incoming data. The serial bit stream should be encoded so as to provide DC balance and limited run length by

an 8B/10B encoding scheme. For proper operation, the baud rate of the data stream to be recovered should be

within +200 ppm of ten (or twenty) times the RFC frequency. For example, Gigabit Ethernet systems would use

125MHz oscillators with a ±100ppm accuracy resulting in ±200 ppm between VSC7185 pairs.

Deserializer

The recovered serial bit stream is converted into a 5-bit parallel output character. The VSC7185 provides

complementary SSTL-2 recovered clocks, RCi0 and RCi1, which are at 1/10th of the serial baud rate. The

clocks are generated by dividing down the high-speed recovered clock which is phase-locked to the serial data.

The serial data is retimed, deserialized and output on RXi(0:4).

If serial input data is not present, or does not meet the required baud rate, the VSC7185 will continue to

produce a recovered clock so that downstream logic may continue to function. The RCi0/RCi1 output frequency

under these circumstances will differ from its expected frequency by no more than +1%.

The receiver drives four sets of 5-pin RX data stable around the edges of RCi1 or RCi0. This is the case

when RSYN=0 (see Figure 2). When RSYN=1, the receive side timing and the transmit side timing are sym-

metrical in that the ASIC section receiving data from the RXi(0:4) buses may alternatively receive data from the

ASIC section driving the TXi(0:4) buses. In this mode, RXi(0:4) transition with the rising and falling edges of

RCi0 and RCi1.

Word Alignment

The VSC7185 provides 7-bit comma character recognition and data word alignment. Word synchronization

is enabled on all channels when SYNC=1. The serial data is converted back into the original 10-bit wide data

and recognizes the presence of the “Comma” pattern. This pattern is “0011111XXX”, where the leading zero

corresponds to the first bit received. The comma sequence is not contained in any normal 8B/10B coded data

character or pair of adjacent characters. It occurs only within special characters, known as K28.1, K28.5 and

K28.7, which are defined for synchronization purposes. When SYNC=1 and an improperly aligned comma is

encountered, the recovered clock is stretched, never slivered, so that the comma character and recovered clocks

are aligned properly to RXi(0:4). This results in proper character and word alignment.

When the parallel data alignment changes in response to a improperly aligned comma pattern, data which

would have been presented on the parallel output port prior to the comma character may be lost. The comma

character itself and data subsequent to the comma character will always be output correctly and properly

aligned. When SYNC=0, the current alignment of the serial data is maintained indefinitely, regardless of data

pattern.

G52324-0, Rev. 3.0

8/28/00

VITESSE

SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

Page 3

VITESSE

SEMICONDUCTOR CORPORATION

Preliminary Data Sheet

VSC7185

Quad Transceiver for

Gigabit Ethernet and Fibre Channel

Loopback Operation

Loopback operation is controlled by PLUP (Parallel Loopback) and SLPN (Serial Loopback) as shown in

Table 1. When PLUP=0 and SLPN=1 the part is configured for normal operation. When PLUP=1 and SLPN=1,

SOi is internally looped to SIi and the SOi outputs are held HIGH. When PLUP=0 and SLPN=0, SIi is looped to

SOi after retiming in the clock recovery unit. Although retiming removes much of the input jitter, the SOi out-

puts may not meet jitter specifications listed in the “Transmitter AC Specifications” due to low frequency jitter

transfer from SIi to SOi. When PLUP=1 and SLPN=0 (both loopback paths are active) the clock recovery unit

is used to retime the internally looped SOi data. The SIi inputs are looped directly to the SOi outputs without

retiming. Jitter on SOi in this mode of operation will depend heavily on SIi jitter, and again the SOi outputs may

not meet jitter specifications. The remote receiver will see the total jitter accumulation across both the incoming

and outgoing serial links.

Table 1: Loopback Selection

PLUP

LOW

HIGH

SLPN

LOW

HIGH

LOW

HIGH

Transmitter Source

Receiver

(Retimed)

Transmitter

Receiver

(Not Retimed)

HIGH

Receiver Source

Receiver

Transmitter

JTAG Access Port

A JTAG access port is provided to assist in board-level testing. Through this port most pins can be observed

or controlled and all TTL outputs can be tri-stated. A full description of the JTAG functions on this device is

available in “VSC7185 JTAG Access Port Functionality.” Circuits designed exclusively for the HDMP-1685A

will automatically disable the JTAG port. Table 7 (Pinout Definitions) in this datasheet shows the proper con-

nections for either HDMP-1685A emulation or for JTAG functionality (in parentheses).

G52324-0, Rev. 3.0

8/28/00

VITESSE

SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

Page 5

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