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DS-11802D4-483Y

Description
Digital to Synchro or Resolver, CDIP28, CERAMIC, DDIP-28
CategoryAnalog mixed-signal IC    converter   
File Size338KB,8 Pages
ManufacturerData Device Corporation
Download Datasheet Parametric View All

DS-11802D4-483Y Overview

Digital to Synchro or Resolver, CDIP28, CERAMIC, DDIP-28

DS-11802D4-483Y Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerData Device Corporation
Parts packaging codeDIP
package instructionCERAMIC, DDIP-28
Contacts28
Reach Compliance Codecompliant
ECCN codeEAR99
Maximum angular accuracy4 arc min
Converter typeDIGITAL TO SYNCHRO OR RESOLVER
JESD-30 codeR-CDIP-T28
JESD-609 codee0
length35.56 mm
Maximum negative supply voltage-16.5 V
Minimum negative supply voltage-13.5 V
Nominal negative supply voltage-15 V
Number of digits16
Number of functions1
Number of terminals28
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeDIP
Package shapeRECTANGULAR
Package formIN-LINE
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Certification statusNot Qualified
Maximum seat height5.82 mm
Signal/output frequency1000 Hz
Maximum supply voltage16.5 V
Minimum supply voltage13.5 V
Nominal supply voltage15 V
surface mountNO
Temperature levelMILITARY
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width15.24 mm
DS-11802
FOUR QUADRANT MULTIPLYING SIN/COS DAC,
MICROPROCESSOR COMPATIBLE, 16-BIT HYBRID
DESCRIPTION
The DS-11802 is a small size, high
accuracy, 16-bit digital-to-sine/cosine
converter. Available in accuracies up
to 1 arc minute, the DS-11802 is con-
tained in a 28-pin DDIP and requires
+15 Vdc and -15 Vdc power supplies.
The reference input is buffered
through an op-amp to minimize load-
ing on the input signal and can accept
up to ±10 V peak. The DS-11802 is
pin programmable for gains of 0.5,
1.0, and 2.0. Two registers for the
input of the 16-bit (CMOS/TTL) natur-
al binary angle data allow for compat-
ibility with an 8-bit or 16-bit data bus.
Internally, the DS-11802 has a multi-
plying digital-to-sin/cos converter
consisting of two function generators
and a quadrant select network.
Quadrant information is available
from the two most significant bits
(MSBs). The two function generators
use the remaining angular data along
with the buffered reference voltage.
Similar to a multiplying DAC (digital-
to-analog converter), the DS-11802
uses high-accuracy resistive ladder
networks and solid-state switching to
control the attenuation of the refer-
ence voltage. The output buffer ampli-
fiers allow for up to 2 mA output drive.
FEATURES
28-Pin Ceramic DDIP Package
1 Arc Minute Accuracy
0.03% Radius Accuracy
Microprocessor Compatible -
8- and 16-Bit
APPLICATIONS
Due to the high accuracy, high reliabil-
ity, small size, low power consumption
and MIL-PRF-38534 processing avail-
able, the DS-11802 is suitable for
industrial and military ground or avion-
ic applications. Possible applications
include digital remote positioning,
resolver angle simulation, flight train-
ers, flight instrumentation, radar and
navigational systems, and PPI dis-
plays including moving target indica-
tors. Other applications are syn-
chro/resolver system development
and testing, and wraparound test of
synchro/resolver-to-digital converters.
Double-Buffered Inputs
Pin-Programmable Gain -
0.5, 1.0 or 2.0
Buffered Reference Input
DC-Coupled Reference and
Outputs
Requires Only ±15 V Power
Supplies
TTL and CMOS Compatible
Pin-for-Pin Replacement for
Natel’s HDSC2306
26
+V –V
S
S
27
HBE 9
(MSB) B1 1
B2 2
B3 3
B4 4
B5 5
B6 6
INPUT BUFFERS
B7 7
B8 8
16-BIT
HOLDING
REGISTER
16-BIT
HIGH
ACCURACY
MULTIPLYING
DIGITAL
TO SIN / COS
CONVERTER
CK
Q1
8-BIT
INPUT
REGISTER
D
BIT 1
(MSB)
28 SINθ
B9 11
B10 12
B11 13
B12 14
B13 15
B14 16
B15 17
(LSB) B16 18
BUFFER
AMPLIFIERS
21 COSθ
8-BIT
INPUT
REGISTER
D
Q16
CK
CK
BIT16
(LSB)
LBE 10
LDC 19
REFERENCE
CONDITIONER
25
GND
20
VIN
22
23
TP1 GC1
24
GC2
FIGURE 1. DS-11802 BLOCK DIAGRAM
©
1996, 1999 Data Device Corporation
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