DPSD256MX4XY5-DPXXNP13 datasheet, PDF

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DPSD256MX4XY5-DPXXNP13: DescriptionSynchronous DRAM, 256MX4, CMOS, PDSO54, STACKED, TSOP2-54; Categorystorage storage; File Size140KB，2 Pages; ManufacturerB&B Electronics Manufacturing Company

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DPSD256MX4XY5-DPXXNP13 Overview

Synchronous DRAM, 256MX4, CMOS, PDSO54, STACKED, TSOP2-54

DPSD256MX4XY5-DPXXNP13 Parametric

Parameter Name	Attribute value
Maker	B&B Electronics Manufacturing Company
Parts packaging code	TSOP2
package instruction	ATSOP,
Contacts	54
Reach Compliance Code	unknown
ECCN code	EAR99
access mode	FOUR BANK PAGE BURST
Other features	AUTO/SELF REFRESH
JESD-30 code	R-PDSO-G54
memory density	1073741824 bit
Memory IC Type	SYNCHRONOUS DRAM
memory width	4
Number of functions	1
Number of ports	1
Number of terminals	54
word count	268435456 words
character code	256000000
Operating mode	SYNCHRONOUS
organize	256MX4
Package body material	PLASTIC/EPOXY
encapsulated code	ATSOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, PIGGYBACK, THIN PROFILE
Certification status	Not Qualified
Maximum seat height	2.59 mm
self refresh	YES
surface mount	YES
technology	CMOS
Terminal form	GULL WING
Terminal pitch	0.8 mm
Terminal location	DUAL

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ADVANCE D COM P ON E NTS PACKAG I NG

1 Gigabit Synchronous DRAM

DPSD256MX4XY5

DESCRIPTION:

The Memory Stack™ series is a family of interchangeable memory devices. The 1 Gigabit Syncronous DRAM assembly

utilizes the space saving LP-Stack™ technology to increase memory density. This stack is constructed with two 512Mb

(128M x 4) SDRAMs.

This 1Gb LP-Stack™ has been designed to fit in the

same footprint as the 512Mb (128M x 4) SDRAM

TSOPII monolithic. This stack allows for system upgrade

while providing an alternative low cost memory solution.

FEATURES:

•

Electrical characteristics meet semiconductor

manufacturers’ datasheets

Memory organization:

(2) 512Mb memory devices. Each device arranged

as 128M x 4 bits (32M x 4 bits x 4 banks)

Memory stack organization:

256M x 4 bits (64M x 4 bits x 4 banks)

•

JEDEC approved, 2 Rank stack pinout and

footprint (with 2 CSs, 1 CKE)

Optimized for RDIMMs

IPC-A-610, class 2, manufacturing standards

Lead free manufacturing process

Package: 54-Pin TSOPII stack

PIN-OUT DIAGRAM

VCC

N.C.

VCCQ

N.C.

DQ0

VSSQ

N.C.

VCCQ

N.C.

DQ1

VSSQ

N.C.

VCC

CS1

CAS

RAS

CS0

BA0

BA1

A10

VCC

VSS

N.C.

VSSQ

N.C.

DQ3

VCCQ

N.C.

VSSQ

N.C.

DQ2

VCCQ

N.C.

VSS

N.C.

DQM

CLK

CKE

A12/N.C.*

A11

VSS

•

(TOP VIEW)

* N.C. on 4K Refresh Stacks.

A0-A12

BA0, BA1

DQ0-DQ3

CAS

RAS

DQM

CKE

CLK

CS0, CS1

CCQ

SSQ

PIN NAMES

Row Address:

Column Address:

Data In/Data Out

A0-A12

A0-A9, A11, A12

FUNCTIONAL BLOCK DIAGRAM

CS1

CS0

RAS

CAS

CLK

DQM

CKE

A0-A12

BA0,BA1

(32M x 4bit x 4 bank)

Column Address Strobe

Row Address Strobe

Data Write Enable

Data Input/Output Mask

Clock Enable

System Clock

Chip Selects

Power Supply/Ground

Data Output Power/Ground

No Connect

512 Mb SDRAM

(32M x 4 bit x 4 bank)

Bank Select Address

DQ0-DQ3

30A215-10

REV. C 6/03

This document contains information on a product that is currently released to production at DPAC Technologies.

DPAC reserves the right to change products or specifications herein without prior notice.

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Shortcut: 00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W

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