XC3020-125PC84C datasheet, PDF

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XC3020-125PC84C: DescriptionField Programmable Gate Array, 64 CLBs, 1000 Gates, 125MHz, 64-Cell, CMOS, PQCC84, PLASTIC, LCC-84; CategoryProgrammable logic devices Programmable logic; File Size731KB，76 Pages; ManufacturerXILINX; Websitehttps://www.xilinx.com/

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XC3020-125PC84C Overview

Field Programmable Gate Array, 64 CLBs, 1000 Gates, 125MHz, 64-Cell, CMOS, PQCC84, PLASTIC, LCC-84

XC3020-125PC84C Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	XILINX
Parts packaging code	LCC
package instruction	PLASTIC, LCC-84
Contacts	84
Reach Compliance Code	unknown
Other features	256 FLIP-FLOPS; TYP. GATES = 1000-1500; POWER-DOWN SUPPLY CURRENT = 50UA
maximum clock frequency	125 MHz
Combined latency of CLB-Max	5.5 ns
JESD-30 code	S-PQCC-J84
JESD-609 code	e0
length	29.3116 mm
Humidity sensitivity level	3
Configurable number of logic blocks	64
Equivalent number of gates	1000
Number of entries	64
Number of logical units	64
Output times	64
Number of terminals	84
Maximum operating temperature	85 °C
Minimum operating temperature
organize	64 CLBS, 1000 GATES
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Encapsulate equivalent code	LDCC84,1.2SQ
Package shape	SQUARE
Package form	CHIP CARRIER
power supply	5 V
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
Maximum seat height	5.08 mm
Maximum supply voltage	5.25 V
Minimum supply voltage	4.75 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	OTHER
Terminal surface	Tin/Lead (Sn85Pb15)
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
width	29.3116 mm

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XC3000 Series

Field Programmable Gate Arrays

(XC3000A/L, XC3100A/L)

November 9, 1998 (Version 3.1)

Product Description

•

Complete Development System

- Schematic capture, automatic place and route

- Logic and timing simulation

- Interactive design editor for design optimization

- Timing calculator

- Interfaces to popular design environments like

Viewlogic, Cadence, Mentor Graphics, and others

Features

•

Complete line of four related Field Programmable Gate

Array product families

- XC3000A, XC3000L, XC3100A, XC3100L

Ideal for a wide range of custom VLSI design tasks

- Replaces TTL, MSI, and other PLD logic

- Integrates complete sub-systems into a single

package

- Avoids the NRE, time delay, and risk of conventional

masked gate arrays

High-performance CMOS static memory technology

- Guaranteed toggle rates of 70 to 370 MHz, logic

delays from 7 to 1.5 ns

- System clock speeds over 85 MHz

- Low quiescent and active power consumption

Flexible FPGA architecture

- Compatible arrays ranging from 1,000 to 7,500 gate

complexity

- Extensive register, combinatorial, and I/O

capabilities

- High fan-out signal distribution, low-skew clock nets

- Internal 3-state bus capabilities

- TTL or CMOS input thresholds

- On-chip crystal oscillator amplifier

Unlimited reprogrammability

- Easy design iteration

- In-system logic changes

Extensive packaging options

- Over 20 different packages

- Plastic and ceramic surface-mount and pin-grid-

array packages

- Thin and Very Thin Quad Flat Pack (TQFP and

VQFP) options

Ready for volume production

- Standard, off-the-shelf product availability

- 100% factory pre-tested devices

- Excellent reliability record

Device

XC3020A, 3020L, 3120A

XC3030A, 3030L, 3130A

XC3042A, 3042L, 3142A, 3142L

XC3064A, 3064L, 3164A

XC3090A, 3090L, 3190A, 3190L

XC3195A

Max Logic

Gates

1,500

2,000

3,000

4,500

6,000

7,500

Typical Gate

CLBs

Range

1,000 - 1,500

1,500 - 2,000

2,000 - 3,000

3,500 - 4,500

5,000 - 6,000

6,500 - 7,500

100

144

224

320

484

•

Additional XC3100A Features

•

Ultra-high-speed FPGA family with six members

- 50-85 MHz system clock rates

- 190 to 370 MHz guaranteed flip-flop toggle rates

- 1.55 to 4.1 ns logic delays

High-end additional family member in the 22 X 22 CLB

array-size XC3195A device

8 mA output sink current and 8 mA source current

Maximum power-down and quiescent current is 5 mA

100% architecture and pin-out compatible with other

XC3000 families

Software and bitstream compatible with the XC3000,

XC3000A, and XC3000L families

•

XC3100A combines the features of the XC3000A and

XC3100 families:

•

Additional interconnect resources for TBUFs and CE

inputs

Error checking of the configuration bitstream

Soft startup holds all outputs slew-rate limited during

initial power-up

More advanced CMOS process

•

Low-Voltage Versions Available

•

Low-voltage devices function at 3.0 - 3.6 V

XC3000L - Low-voltage versions of XC3000A devices

XC3100L - Low-voltage versions of XC3100A devices

•

Array

8x8

10 x 10

12 x 12

16 x 14

16 x 20

22 x 22

User I/Os

Flip-Flops

Max

256

120

144

176

360

480

688

928

1,320

Horizontal

Longlines

Configuration

Data Bits

14,779

22,176

30,784

46,064

64,160

94,984

November 9, 1998 (Version 3.1)

7-3

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