X25323S8I datasheet, PDF - EEWORLD Datasheet

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X25323S8I: DescriptionPower Supply Management Circuit, Fixed, 1 Channel, PDSO8, PLASTIC, SOIC-8; CategoryPower/power management The power supply circuit; File Size115KB，20 Pages; ManufacturerXicor Inc.

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X25323S8I Overview

Power Supply Management Circuit, Fixed, 1 Channel, PDSO8, PLASTIC, SOIC-8

X25323S8I Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Xicor Inc.
package instruction	PLASTIC, SOIC-8
Reach Compliance Code	unknown
Adjustable threshold	NO
Analog Integrated Circuits - Other Types	POWER SUPPLY MANAGEMENT CIRCUIT
JESD-30 code	R-PDSO-G8
JESD-609 code	e0
length	4.9 mm
Number of channels	1
Number of functions	1
Number of terminals	8
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
Maximum seat height	1.75 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	3.9 mm

X25323S8I Preview

64K

32K

16K

FEATURES

X25643/45

X25323/25

X25163/65

DESCRIPTION

8K x 8 Bit

4K x 8 Bit

2K x 8 Bit

Programmable Watchdog Timer & V

Supervisory Circuit w/Serial E

PROM

• Programmable Watchdog Timer

• Low Vcc Detection and Reset Assertion

—Reset Signal Valid to Vcc=1V

• Save Critical Data With Block Lock

Protection

—Block Lock

Protect 0, 1/4, 1/2 or all of

Serial E

PROM Memory Array

• In Circuit Programmable ROM Mode

• Long Battery Life With Low Power Consumption

—<50

A Max Standby Current, Watchdog On

—<1

A Max Standby Current, Watchdog Off

—<5mA Max Active Current during Write

—<400

A Max Active Current during Read

• 1.8V to 3.6V, 2.7V to 5.5V and 4.5V to 5.5V Power

Supply Operation

• 2MHz Clock Rate

• Minimize Programming Time

—32 Byte Page Write Mode

—Self-Timed Write Cycle

—5ms Write Cycle Time (Typical)

• SPI Modes (0,0 & 1,1)

• Built-in Inadvertent Write Protection

—Power-Up/Power-Down Protection Circuitry

—Write Enable Latch

—Write Protect Pin

• High Reliability

• Available Packages

—14-Lead SOIC (X2564x)

—14-Lead TSSOP (X2532x, X2516x)

—8-Lead SOIC (X2532x, X2516x)

BLOCK DIAGRAM

SCK

DATA

COMMAND

DECODE &

CONTROL

LOGIC

RESET

CONTROL

X - DECODE

LOGIC

These devices combine three popular functions, Watch-

dog Timer, Supply Voltage Supervision, and Serial

PROM Memory in one package. This combination low-

ers system cost, reduces board space requirements, and

increases reliability.

The Watchdog Timer provides an independent protection

mechanism for microcontrollers. During a system failure,

the device will respond with a RESET/RESET signal

after a selectable time-out interval. The user selects the

interval from three preset values. Once selected, the

interval does not change, even after cycling the power.

The user’s system is protected from low voltage condi-

tions by the device’s low Vcc detection circuitry. When

Vcc falls below the minimum Vcc trip point, the system is

reset. RESET/RESET is asserted until Vcc returns to

proper operating levels and stabilizes.

The memory portion of the device is a CMOS Serial

PROM array with Xicor’s Block Lock

Protection. The

array is internally organized as x 8. The device features a

Serial Peripheral Interface (SPI) and software protocol

allowing operation on a simple four-wire bus.

The device utilizes Xicor’s proprietary Direct Write

cell,

providing a minimum endurance of 100,000 cycles per

sector and a minimum data retention of 100 years.

PAGE DECODE LOGIC

SERIAL

PROM

ARRAY

RESET/RESET

STATUS

LOW

VOLTAGE

SENSE

WATCHDOG

TIMER

PROGRAMMING,

BLOCK LOCK &

ICP ROM CONTROL

HIGH

VOLTAGE

CONTROL

Characteristics subject to change without notice

7036 FRM 01

Xicor, Inc. 1994, 1995, 1996 Patents Pending

7049 -1.1 9/11/97 T1/C0/D0 SH

X25643/45

X25323/25

X25163/65

PIN DESCRIPTIONS

Serial Output (SO)

SO is a push/pull serial data output pin. During a read

cycle, data is shifted out on this pin. Data is clocked out by

the falling edge of the serial clock.

Serial Input (SI)

SI is a serial data input pin. All opcodes, byte addresses,

and data to be written to the memory are input on this pin.

Data is latched by the rising edge of the serial clock.

Serial Clock (SCK)

The Serial Clock controls the serial bus timing for data

input and output. Opcodes, addresses, or data present on

the SI pin are latched on the rising edge of the clock input,

while data on the SO pin change after the falling edge of

the clock input.

Chip Select (CS)

When CS is HIGH, the device is deselected and the SO

output pin is at high impedance and unless a nonvolatile

write cycle is underway, the device will be in the standby

power mode. CS LOW enables the device, placing it in

the active power mode. It should be noted that after

power-up, a HIGH to LOW transition on CS is required

prior to the start of any operation.

Write Protect (WP)

When WP is low and the nonvolatile bit WPEN is “1”,

nonvolatile writes to the device’s Status Register are

disabled, but the part otherwise functions normally. When

WP is held high, all functions, including nonvolatile writes

to the Status Register operate normally. If an internal

Status Register Write Cycle has already been initiated,

WP going low while WPEN is a “1” will have no effect on

this write. Subsequent write attempts to the Status

The WP pin function is blocked when the WPEN bit in the

Status Register is “0”. This allows the user to install the

device in a system with WP pin grounded and still be able

to program the Status Register. The WP pin functions will

be enabled when the WPEN bit is set to a “1”.

Reset (RESET/RESET)

RESET/RESET is an active LOW/HIGH, open drain out-

put which goes active whenever Vcc falls below the mini-

mum Vcc sense level. It will remain active until Vcc rises

above the minimum Vcc sense level for 200ms. RESET/

RESET will also go active if the Watchdog Timer is

enabled and CS remains either HIGH or LOW longer than

the selectable Watchdog time-out period. A falling edge of

CS will reset the Watchdog Timer.

PIN CONFIGURATION

14-LEAD SOIC

0.345” SO

VSS

0.244”

8-LEAD SOIC

0.197” WP

VSS

V CC

RESET/RESET

SCK

X25643/45

V CC

RESET/RESET

SCK

Not to Scale

X25323/25

X25163/65

0.244”

14-LEAD TSSOP

0.200” NC

VSS

V CC

RESET/RESET

SCK

7036 FRM 02

X25323/25

X25163/65

0.177”

PIN NAMES

Symbol

SCK

RESET/RESET

Description

Chip Select Input

Serial Output

Serial Input

Serial Clock Input

Program Protect Input

Ground

Supply Voltage

Reset Output

7036 FRM T01

X25643/45

X25323/25

X25163/65

PRINCIPLES OF OPERATION

The device is designed to interface directly with the syn-

chronous Serial Peripheral Interface (SPI) of many popu-

lar microcontroller families.

The device monitors the bus and asserts RESET/RESET

output if there is no bus activity within user programmable

time-out period or the supply voltage falls below a preset

minimum V

trip

. The device contains an 8-bit instruction

clocked in on the rising edge of SCK. CS must be LOW

during the entire operation.

All instructions

(

Table 1), addresses and data are trans-

ferred MSB ﬁrst. Data input on the SI line is latched on the

ﬁrst rising edge of SCK after CS goes LOW. Data is out-

put on the SO line by the falling edge of SCK. SCK is

static, allowing the user to stop the clock and then start it

again to resume operations where left off.

Write Enable Latch

The device contains a Write Enable Latch. This latch must

be SET before a Write Operation is initiated. The WREN

instruction will set the latch and the WRDI instruction will

reset the latch (Figure 3). This latch is automatically reset

upon a power-up condition and after the completion of a

valid Write Cycle.

Status Register

The RDSR instruction provides access to the Status Reg-

ister. The Status Register may be read at any time, even

during a Write Cycle. The Status Register is formatted as

follows:

BL1

The Write-In-Progress (WIP) bit is a volatile, read only bit

and indicates whether the device is busy with an internal

nonvolatile write operation. The WIP bit is read using the

RDSR instruction. When set to a “1”, a nonvolatile write

operation is in progress. When set to a “0”, no write is in

progress.

The Write Enable Latch (WEL) bit indicates the Status of

the Write Enable Latch. When WEL=1, the latch is set

HIGH and when WEL=0 the latch is reset LOW. The WEL

bit is a volatile, read only bit. It can be set by the WREN

instruction and can be reset by the WRDS instruction.

The Block Lock bits, BL0 and BL1, set the level of Block

Lock

Protection. These nonvolatile bits are pro-

grammed using the WRSR instruction and allow the user

to protect one quarter, one half, all or none of the

PROM array. Any portion of the array that is Block Lock

Protected can be read but not written. It will remain pro-

tected until the BL bits are altered to disable Block Lock

Protection of that portion of memory..

Status

Bits

BL1 BL0

Array Addresses Protected

X2564x

None

X2532x

None

X2516x

None

$1800–$1FFF $0C00–$0FFF $0600–$07FF

$1000–$1FFF $0800–$0FFF $0400–$07FF

$0000–$1FFF $0000–$0FFF $0000–$07FF

7036 FRM T03

BL0

WEL

WIP

7036 FRM T02

WPEN FLB

WD1 WD0

Table 1. Instruction Set

Instruction Name

WREN

SFLB

WRDI/RFLB

RSDR

WRSR

READ

WRITE

Instruction Format*

0000 0110

0000 0000

0000 0100

0000 0101

0000 0001

0000 0011

0000 0010

Operation

Set the Write Enable Latch (Enable Write Operations)

Set Flag Bit

Reset the Write Enable Latch/Reset Flag Bit

Read Status Register

Write Status Register(Watchdog,BlockLock,WPEN & Flag Bits)

Read Data from Memory Array Beginning at Selected Address

Write Data to Memory Array Beginning at Selected Address

7036 FRM T04

*Instructions are shown MSB in leftmost position. Instructions are transferred MSB ﬁrst.

X25643/45

X25323/25

X25163/65

The Watchdog Timer bits, WD0 and WD1, select the

Watchdog Time-out Period. These nonvolatile bits are

programmed with the WRSR instruction.

Status Register Bits

WD1

WD0

Watchdog Time-out

(Typical)

1.4 Seconds

600 Milliseconds

200 Milliseconds

Disabled

7036 FRM T05

sent, the data stored in the memory at the selected

address is shifted out on the SO line. The data stored in

memory at the next address can be read sequentially by

continuing to provide clock pulses. The address is auto-

matically incremented to the next higher address after

each byte of data is shifted out. When the highest address

is reached, the address counter rolls over to address

$0000 allowing the read cycle to be continued indeﬁnitely.

The read operation is terminated by taking CS high. Refer

to the Read E

PROM Array Sequence (Figure 1).

To read the Status Register, the CS line is ﬁrst pulled low

to select the device followed by the 8-bit RDSR instruc-

tion. After the RDSR opcode is sent, the contents of the

Status Register are shifted out on the SO line. Refer to

the Read Status Register Sequence (Figure 2).

Write Sequence

Prior to any attempt to write data into the device, the

“Write Enable” Latch (WEL) must ﬁrst be set by issuing

the WREN instruction (Figure 3). CS is ﬁrst taken LOW,

then the WREN instruction is clocked into the device.

After all eight bits of the instruction are transmitted, CS

must then be taken HIGH. If the user continues the Write

Operation without taking CS HIGH after issuing the

WREN instruction, the Write Operation will be ignored.

To write data to the E

PROM memory array, the user then

issues the WRITE instruction followed by the 16 bit

address and then the data to be written. Any unused

address bits are speciﬁed to be “0’s”. The WRITE opera-

tion minimally takes 32 clocks. CS must go low and

remain low for the duration of the operation. If the address

counter reaches the end of a page and the clock contin-

ues, the counter will roll back to the ﬁrst address of the

page and overwrite any data that may have been previ-

ously written.

The read only FLAG bit shows the status of a volatile latch

that can be set and reset by the system using the SFLB

and RFLB instructions. The Flag bit is automatically reset

upon power up.

The nonvolatile WPEN bit is programmed using the

WRSR instruction. This bit works in conjunction with the

WP pin to provide Programmable Hardware Write Protec-

tion (Table 2). When WP is LOW and the WPEN bit is pro-

grammed HIGH, all Status Register Write Operations are

disabled.

In Circuit Programmable ROM Mode

This mechanism protects the Block Lock and Watchdog

bits from inadvertant corruption. It may be used to per-

form an In Circuit Programmable ROM function by hard-

wiring the WP pin to ground, writing and Block Locking

the desired portion of the array to be ROM, and then pro-

gramming the WPEN bit HIGH.

Read Sequence

When reading from the E

PROM memory array, CS is

ﬁrst pulled low to select the device. The 8-bit READ

instruction is transmitted to the device, followed by the 16-

bit address. After the READ opcode and address are

Table 2. Block Protect Matrix

STATUS

WEL

STATUS

WPEN

DEVICE

WP#

BLOCK

PROTECTED

BLOCK

Protected

BLOCK

UNPROTECTED

BLOCK

Protected

Writable

STATUS

WPEN, BL0, BL1

WD0, WD1, BITS

Protected

Writable

7036 FRM T06

X25643/45

X25323/25

X25163/65

For the Page Write Operation (byte or page write) to be

completed, CS can only be brought HIGH after bit 0 of the

last data byte to be written is clocked in. If it is brought

HIGH at any other time, the write operation will not be

completed (Figure 4).

To write to the Status Register, the WRSR instruction is

followed by the data to be written (Figure 5). Data bits 0

and 1 must be “0” .

While the write is in progress following a Status Register

or E

PROM Sequence, the Status Register may be read

to check the WIP bit. During this time the WIP bit will be

high.

RESET/RESET Operation

The RESET (X25xx3) output is designed to go LOW

whenever V

has dropped below the minimum trip point

and/or the Watchdog timer has reached its programmable

time-out limit.

The RESET (X25xx5) output is designed to go HIGH

whenever V

has dropped below the minimum trip point

and/or the watchdog timer has reached its programmable

time-out limit.

Figure 1. Read E

PROM Array Sequence

The RESET/RESET output is an open drain output and

requires a pull up resistor.

Operational Notes

The device powers-up in the following state:

• The device is in the low power standby state.

• A HIGH to LOW transition on CS is required to enter an

active state and receive an instruction.

• SO pin is high impedance.

• The Write Enable Latch is reset.

• The Flag Bit is reset.

• Reset Signal is active for t

PURST

Data Protection

The following circuitry has been included to prevent inad-

vertent writes:

• A WREN instruction must be issued to set the Write

Enable Latch.

• CS must come HIGH at the proper clock count in order

to start a nonvolatile write cycle.

SCK

20 21 22 23 24 25

26 27 28 29 30

INSTRUCTION

16 BIT ADDRESS

15 14 13

DATA OUT

HIGH IMPEDANCE

MSB

7036 FRM 03

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X25323S8I Related Products

	X25323S8I	X25165V14	X25645S14I	X25323S8	X25163V14I	X25163S8I	X25643S14	X25643S14I
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Is it Rohs certified?	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible
Maker	Xicor Inc.	Xicor Inc.	Xicor Inc.	Xicor Inc.	Xicor Inc.	Xicor Inc.	Xicor Inc.	Xicor Inc.
package instruction	PLASTIC, SOIC-8	PLASTIC, TSSOP-14	PLASTIC, SOIC-14	PLASTIC, SOIC-8	PLASTIC, TSSOP-14	PLASTIC, SOIC-8	PLASTIC, SOIC-14	PLASTIC, SOIC-14
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown	unknown	unknown	unknown
Adjustable threshold	NO	NO	NO	NO	NO	NO	NO	NO
Analog Integrated Circuits - Other Types	POWER SUPPLY MANAGEMENT CIRCUIT	POWER SUPPLY MANAGEMENT CIRCUIT	POWER SUPPLY MANAGEMENT CIRCUIT	POWER SUPPLY MANAGEMENT CIRCUIT	POWER SUPPLY MANAGEMENT CIRCUIT	POWER SUPPLY MANAGEMENT CIRCUIT	POWER SUPPLY MANAGEMENT CIRCUIT	POWER SUPPLY MANAGEMENT CIRCUIT
JESD-30 code	R-PDSO-G8	R-PDSO-G14	R-PDSO-G14	R-PDSO-G8	R-PDSO-G14	R-PDSO-G8	R-PDSO-G14	R-PDSO-G14
JESD-609 code	e0	e0	e0	e0	e0	e0	e0	e0
length	4.9 mm	5 mm	8.65 mm	4.9 mm	5 mm	4.9 mm	8.65 mm	8.65 mm
Number of channels	1	1	1	1	1	1	1	1
Number of functions	1	1	1	1	1	1	1	1
Number of terminals	8	14	14	8	14	8	14	14
Maximum operating temperature	85 °C	70 °C	85 °C	70 °C	85 °C	85 °C	70 °C	85 °C
Minimum operating temperature	-40 °C	-	-40 °C	-	-40 °C	-40 °C	-	-40 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	SOP	TSSOP	SOP	SOP	TSSOP	SOP	SOP	SOP
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.75 mm	1.2 mm	1.75 mm	1.75 mm	1.2 mm	1.75 mm	1.75 mm	1.75 mm
Maximum supply voltage (Vsup)	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V
Minimum supply voltage (Vsup)	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V
Nominal supply voltage (Vsup)	5 V	5 V	5 V	5 V	5 V	5 V	5 V	5 V
surface mount	YES	YES	YES	YES	YES	YES	YES	YES
Temperature level	INDUSTRIAL	COMMERCIAL	INDUSTRIAL	COMMERCIAL	INDUSTRIAL	INDUSTRIAL	COMMERCIAL	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING
Terminal pitch	1.27 mm	0.65 mm	1.27 mm	1.27 mm	0.65 mm	1.27 mm	1.27 mm	1.27 mm
Terminal location	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
width	3.9 mm	4.4 mm	3.9 mm	3.9 mm	4.4 mm	3.9 mm	3.9 mm	3.9 mm

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