IS61QDB24M18-250M3I datasheet, PDF

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IS61QDB24M18-250M3I: DescriptionDDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, LFBGA-165; Categorystorage storage; File Size635KB，28 Pages; ManufacturerIntegrated Silicon Solution ( ISSI )

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IS61QDB24M18-250M3I Overview

DDR SRAM, 4MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1 MM PITCH, LFBGA-165

IS61QDB24M18-250M3I Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Integrated Silicon Solution ( ISSI )
Parts packaging code	BGA
package instruction	15 X 17 MM, 1 MM PITCH, LFBGA-165
Contacts	165
Reach Compliance Code	compliant
ECCN code	3A991.B.2.A
Maximum access time	0.45 ns
Other features	PIPELINED ARCHITECTURE
Maximum clock frequency (fCLK)	250 MHz
I/O type	SEPARATE
JESD-30 code	R-PBGA-B165
JESD-609 code	e0
length	17 mm
memory density	75497472 bit
Memory IC Type	DDR SRAM
memory width	18
Number of functions	1
Number of terminals	165
word count	4194304 words
character code	4000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	4MX18
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	LBGA
Encapsulate equivalent code	BGA165,11X15,40
Package shape	RECTANGULAR
Package form	GRID ARRAY, LOW PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	1.5/1.8,1.8 V
Certification status	Not Qualified
Maximum seat height	1.4 mm
Minimum standby current	1.7 V
Maximum slew rate	0.75 mA
Maximum supply voltage (Vsup)	1.89 V
Minimum supply voltage (Vsup)	1.71 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	TIN LEAD
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	15 mm

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72 Mb (2M x 36 & 4M x 18)

QUAD (Burst of 2) Synchronous SRAMs

Features

•

x 36 or

x 18.

• On-chip delay-locked loop (DLL) for wide data

valid window.

• Separate read and write ports with concurrent

read and write operations.

• Synchronous pipeline read with early write oper-

ation.

• Double data rate (DDR) interface for read and

write input ports.

• Fixed 2-bit burst for read and write operations.

• Clock stop support.

• Two input clocks (K and K) for address and con-

trol registering at rising edges only.

• Two input clocks (C and C) for data output con-

trol.

• Two echo clocks (CQ

and CQ)

that are delivered

simultaneously with data.

• +1.8V core power supply and 1.5, 1.8V V

DDQ

used with 0.75, 0.9V V

REF

• HSTL input and output levels.

• Registered addresses, write and read controls,

byte writes, data in, and data outputs.

• Full data coherency.

• Boundary scan using limited set of JTAG 1149.1

functions.

• Byte write capability.

• Fine ball grid array (FBGA) package

- 15mm x 17mm body size

- 1mm pitch

- 165-ball (11 x 15) array

• Programmable impedance output drivers via 5x

user-supplied precision resistor.

March

2011

Description

The

72Mb IS61QDB22M36

and

IS61QDB24M18

are synchronous, high-perfor-

mance CMOS static random access memory

(SRAM) devices. These SRAMs have separate I/Os,

eliminating the need for high-speed bus turnaround.

The rising edge of K clock initiates the read/write

operation, and all internal operations are self-timed.

Refer to the

Timing Reference Diagram for Truth

Table

on page

for a description of the basic opera-

tions of these SRAMs.

The input address bus operates at double data rate.

The following are registered internally on the rising

edge of the K clock:

•

Read address

Read enable

Write enable

Byte writes

Data-in for early writes

• Write address

• Byte writes

• Data-in for second burst addresses

Byte writes can change with the corresponding data-

in to enable or disable writes on a per-byte basis. An

internal write buffer enables the data-ins to be regis-

tered half a cycle earlier than the write address. The

first data-in burst is clocked at the same time as the

write command signal, and the second burst is timed

to the following rising edge of the K clock.

During the burst read operation, the data-outs from

the first burst are updated from output registers off

the second rising edge of the C clock (1.5 cycles

later). The data-outs from the second burst are

updated with the third rising edge of the C clock. The

K and K clocks are used to time the data-outs when-

ever the C and C clocks are tied high.

The device is operated with a single +1.8V power

supply and is compatible with HSTL I/O interfaces.

The following are registered on the rising edge of

the K clock:

notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-

est version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be ex-

pected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon

Solution, Inc. receives written assurance to its satisfaction, that:

a.) the risk of injury or damage has been minimized;

b.) the user assume all such risks; and

c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances

Integrated Silicon Solution, Inc.

Rev.

03/31/2011

372 Mb (2M x 36 & 4M x 18)

QUAD (Burst of 2) Synchronous SRAMs

ISSI

During a write, the byte writes independently control which byte of any of the two burst addresses is written

(see

X18/X36 Write Truth Tables

on page

and

Timing Reference Diagram for Truth Table

on page

8).

Whenever a write is disabled (W is high at the rising edge of K), data is not written into the memory.

RQ Programmable Impedance

An external resistor, RQ, must be connected between the ZQ pin on the SRAM and V

to enable the SRAM

to adjust its output driver impedance. The value of RQ must be 5x the value of the intended line impedance

driven by the SRAM. For example, an RQ of 250Ω results in a driver impedance of 50Ω. The allowable range

of RQ to guarantee impedance matching is between 175Ω and 350Ω, with the tolerance described in

Programmable Impedance Output Driver DC Electrical Characteristics

on page 13. The RQ resistor should

be placed less than two inches away from the ZQ ball on the SRAM module. The capacitance of the loaded

ZQ trace must be less than 3 pF.

The ZQ pin can also be directly connected to V

DDQ

to obtain a minimum impedance setting. ZQ must never

be connected to V

Programmable Impedance and Power-Up Requirements

Periodic readjustment of the output driver impedance is necessary as the impedance is greatly affected by

drifts in supply voltage and temperature. At power-up, the driver impedance is in the middle of allowable

impedances values. The final impedance value is achieved within 1024 clock cycles.

Single Clock Mode

This device can be also operated in single-clock mode. In this case, C and C are both connected high at

power-up and must never change. Under this condition, K and K will control the output timings.

Either clock pair must have both polarities switching and must never connect to V

REF

, as they are not differ-

ential clocks

Depth Expansion

Separate input and output ports enable easy depth expansion, as each port can be selected and deselected

independently. Read and write operations can occur simultaneously without affecting each other. Also, all

pending read and write transactions are always completed prior to deselecting the corresponding port.

In the following application example, the second pair of C and C clocks is delayed such that the return data

meets the data setup and hold times at the

memory controller.

Integrated Silicon Solution, Inc.

Rev.

03/31/2011

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