M29W040
4 Mbit (512Kb x8, Uniform Block)
Low Voltage Single Supply Flash Memory
NOT FOR NEW DESIGN
M29W040 is replaced by the M29W040B
2.7V to 3.6V SUPPLY VOLTAGE for
PROGRAM, ERASE and READ OPERATIONS
FAST ACCESS TIME: 100ns
BYTE PROGRAMMING TIME: 12µs typical
ERASE TIME
– Block: 1.5 sec typical
– Chip: 2.5 sec typical
PROGRAM/ERASE CONTROLLER (P/E.C.)
– Program Byte-by-Byte
– Data Polling and Toggle bits Protocol for
P/E.C. Status
MEMORY ERASE in BLOCKS
– 8 Uniform Blocks of 64 KBytes each
– Block Protection
– Multiblock Erase
ERASE SUSPEND and RESUME MODES
LOW POWER CONSUMPTION
– Read mode: 8mA typical (at 12MHz)
– Stand-by mode: 20µA typical
– Automatic Stand-by mode
POWER DOWN SOFTWARE COMMAND
– Power-down mode: 1µA typical
100,000 PROGRAM/ERASE CYCLES per
BLOCK
20 YEARS DATA RETENTION
– Defectivity below 1ppm/year
ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code: E3h
Table 1. Signal Names
A0-A18
DQ0-DQ7
E
G
W
V
CC
V
SS
Address Inputs
Data Input / Outputs
Chip Enable
Output Enable
Write Enable
Supply Voltage
Ground
PLCC32 (K)
TSOP32 (N)
8 x 20mm
TSOP32 (NZ)
8 x 14mm
Figure 1. Logic Diagram
VCC
19
A0-A18
8
DQ0-DQ7
W
E
G
M29W040
VSS
AI02074
November 1999
This is information on a product still in productionbut not recommended for new designs.
1/31
M29W040
Figure 2A. LCC Pin Connections
Figure 2B. TSOP Pin Connections
1 32
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
A14
A13
A8
A9
A11
G
A10
E
DQ7
9
M29W040
25
17
DQ1
DQ2
VSS
DQ3
DQ4
DQ5
DQ6
AI02075
A11
A9
A8
A13
A14
A17
W
VCC
A18
A16
A15
A12
A7
A6
A5
A4
A12
A15
A16
A18
VCC
W
A17
1
32
8
9
M29W040
(Normal)
25
24
16
17
AI02076
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
A3
Figure 2C. TSOP Reverse Pin Connections
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
A3
1
32
8
9
M29W040
(Reverse)
25
24
16
17
AI02077
A11
A9
A8
A13
A14
A17
W
VCC
A18
A16
A15
A12
A7
A6
A5
A4
DESCRIPTION
The M29W040 is a non-volatile memory that may
be erased electrically at the block level, and pro-
grammed Byte-by-Byte.
The interface is directly compatible with most mi-
croprocessors. PLCC32, TSOP32 (8 x 20mm)and
TSOP32 (8 x 14mm) packages are available. Both
normal and reverse pin outs are available for the
TSOP32 (8 x 20mm) package.
Organisation
The FlashMemory organisationis 512K x8 bits with
Address lines A0-A18 and Data Inputs/Outputs
DQ0-DQ7. Memory control is provided by Chip
Enable, Output Enable and Write Enable Inputs.
Erase and Program are performed through the
internal Program/Erase Controller (P/E.C.).
Data Outputs bits DQ7 and DQ6 provide polling or
toggle signals during Automatic Program or Erase
to indicate the Ready/Busy state of the internal
Program/Erase Controller.
Memory Blocks
Erasure of the memory is in blocks. There are 8
uniform blocks of 64 Kbytes each in the memory
address space. Each block can be programmed
and erased over 100,000 cycles. Each uniform
2/31
M29W040
Table 2. Absolute Maximum Ratings
(1)
Symbol
T
A
T
BIAS
T
STG
V
IO
(2)
Parameter
Ambient Operating Temperature
(3)
Temperature Under Bias
Storage Temperature
Input or Output Voltages
Supply Voltage
A9 Voltage
Value
–40 to 85
–50 to 125
–65 to 150
–0.6 to 5
–0.6 to 5
–0.6 to 13.5
Unit
°
C
°C
°
C
V
V
V
V
CC
V
A9
(2)
Notes:
1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings”
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other
relevant quality documents.
2. Minimum Voltage may undershoot to –2V during transition and for less than 20ns.
3. Depends on range.
block may separately be protected and unpro-
tected against program and erase. Block erasure
may be suspended, while data is read from other
blocks of the memory, and then resumed.
Bus Operations
Seven operations can be performed by the appro-
priate bus cycles, Read Array, Read Electronic
Signature, Output Disable, Standby,Protect Block,
Unprotect Block, and Write the Command of an
Instruction.
Command Interface
Command Bytes can be written to a Command
Interface (C.I.) latch to perform Reading (from the
Array or Electronic Signature), Erasure or Pro-
gramming. For added data protection, command
execution starts after 4 or 6 command cycles. The
first, second, fourth and fifth cycles are used to
input a code sequence to the Command Interface
(C.I.). This sequence is equal for all P/E.C. instruc-
tions. Command itself and its confirmation - if it
applies - are given on the third and fourth or sixth
cycles.
Instructions
Eight instructions are defined to perform Reset,
Read Electronic Signature, Auto Program, Block
Auto Erase, Chip Auto Erase, Block Erase Sus-
pend, Block Erase Resume and Power Down. The
internal Program/EraseController (P/E.C.) handles
all timing and verification of the Program and Erase
instructions and provides Data Polling, Toggle, and
Status data to indicate completion of Program and
Erase Operations.
Instructions are composed of up to six cycles. The
first two cycles input a code sequence to the Com-
mand Interface which is common to all P/E.C.
instructions (see Table 7 for Command Descrip-
tions). The third cycle inputs the instruction set up
command instruction to the Command Interface.
Subsequentcycles output Signature,Block Protec-
tion or the addressed data for Read operations.
For added data protection, the instructions for pro-
gram, and block or chip erase require further com-
mand inputs. For a Program instruction, the fourth
command cycle inputs the address and data to be
programmed. For an Erase instruction (block or
chip), the fourth and fifth cycles input a further code
sequence before the Erase confirm command on
the sixth cycle. Byte programming takes typically
12µs while erase is performed in typically 1.5 sec-
ond.
Erasure of a memory block may be suspended, in
order to read data from another block, and then
resumed. Data Polling, Toggle and Error data may
be read at any time, including during the program-
ming or erase cycles, to monitor the progress of
the operation.When power is first applied or if V
CC
falls below V
LKO
, the command interface is reset to
Read Array.
3/31
M29W040
Table 3. Operations
Operation
Read
Write
Output Disable
Standby
Note:
X = V
IL
or V
IH
E
V
IL
V
IL
V
IL
V
IH
G
V
IL
V
IH
V
IH
X
W
V
IH
V
IL
V
IH
X
DQ0 - DQ7
Data Output
Data Input
Hi-Z
Hi-Z
Table 4. Electronic Signature
Code
Manufact. Code
Device Code
E
V
IL
V
IL
G
V
IL
V
IL
W
V
IH
V
IH
A0
V
IL
V
IH
A1
V
IL
V
IL
A6
V
IL
V
IL
A9
V
ID
V
ID
Other
Addresses
Don’t Care
Don’t Care
DQ0 - DQ7
20h
E3h
Table 5. Block Protection Status
Code
Protected Block
Unprotected Block
E
V
IL
V
IL
G
V
IL
V
IL
W
V
IH
V
IH
A0
V
IL
V
IL
A1
V
IH
V
IH
A6
V
IL
V
IL
A16
SA
SA
A17
SA
SA
A18
SA
SA
Other
Addresses
Don’t Care
Don’t Care
DQ0 - DQ7
01h
00h
Note:
SA = Address of block being checked
DEVICE OPERATION
Signal Descriptions
Address Inputs (A0-A18).
The address inputs for
the memory array are latched during a write opera-
tion. The A9 address input is used also for the
Electronic Signature read and Block Protect veri-
fication. When A9 is raised to V
ID
, either a Read
Manufacturer Code, Read Device Code or Verify
Block Protection is enabled dependingon the com-
bination of levels on A0, A1 and A6. When A0, A1
and A6 are Low, the ElectronicSignature Manufac-
turer code is read, when A0 is High and A1 and A6
are Low, the Device code is read, and when A1 is
High and A0 and A6 are low, the Block Protection
Status with protect/unprotect algorithm is read for
the block addressed by A16, A17, A18.
Data Input/Outputs (DQ0-DQ7).
The data input is
a byte to be programmed or a command written to
the C.I. Both are latched when Chip Enable E and
Write Enable W are active. The data output is from
the memory Array, the Electronic Signature, the
Data Polling bit (DQ7), the Toggle Bit (DQ6), the
Error bit (DQ5) or the Erase Timer bit (DQ3). Ou-
puts are valid when Chip Enable E and Output
Enable G are active. The output is high impedance
when the chip is deselected or the outputs are
disabled.
Chip Enable (E).
The Chip Enable activates the
memory control logic, input buffers, decoders and
sense amplifiers. E High deselectsthe memory and
reduces the power consumption to the standby
level. E can also be used to control writing to the
command register and to the memory array, while
W remains at a low level. Addresses are then
latchedon the falling edge of E while data is latched
on the rising edge of E. The Chip Enable must be
forced to V
ID
during Block Unprotect operations.
Output Enable (G).
The Output Enable gates the
outputs through the data buffers during a read
operation. G must be forced to V
ID
level during
Block Protect and Block Unprotect operations.
Write Enable (W).
This input controls writing to the
Command Register and Address and Data latches.
Addressesare latchedon the fallingedge of W, and
Data Inputs are latched on the rising edge of W.
V
CC
Supply Voltage.
The power supply for all
operations (Read, Program and Erase).
V
SS
Ground.
V
SS
is the reference for all voltage
measurements.
4/31
M29W040
Table 6. Instructions
(1)
Mne.
Instr.
Cyc.
1+
RST
(3,9)
1st Cyc. 2nd Cyc. 3rd Cyc. 4th Cyc. 5th Cyc. 6th Cyc.
Addr.
(2,6)
Data
X
F0h
5555h
AAh
5555h
AAh
5555h
AAh
(2,6)
7th Cyc.
Read Memory Array until a new write cycle is initiated.
Read Array/
Reset
3+
Addr.
(2,6)
Data
2AAAh
55h
2AAAh
55h
2AAAh
55h
2AAAh
5555h
F0h
5555h
90h
5555h
90h
5555h
Read Memory Array until a new write
cycle is initiated.
RSIG
(3)
Read
Electronic
Signature
Read Block
Protection
Addr.
(2,6)
3+
Data
Addr.
(2,6)
Data
Addr.
Read Electronic Signature until a new
write cycle is initiated. See Note 4.
RBP
(3)
3+
Read Block Protection until a new write
cycle is initiated. See Note 5.
Program
Address Read Data Polling or Toggle Bit
until Program completes.
Program
Data
5555h
AAh
5555h
AAh
2AAAh
55h
2AAAh
55h
Block
Address
30h
5555h
10h
Additional
Block
(7)
30h
Note 8
5555h
PG
Program
4
Data
(2,6)
AAh
55h
A0h
BE
Block Erase
6
Addr.
Data
5555h
AAh
5555h
AAh
2AAAh
55h
2AAAh
55h
5555h
80h
5555h
80h
CE
Chip Erase
6
Addr.
(2,6)
Data
ES
Erase
Suspend
1
Addr.
Data
(2,6)
X
B0h
X
30h
5555h
20h
Read until Toggle stops, then read all the data needed from any
uniform block(s) not being erased then Resume Erase.
ER
Erase
Resume
1
Addr.
(2,6)
Data
Read Data Polling or Toggle Bit until Erase completes or Erase
is suspended another time
PD
(10)
Power
Down
1
Addr.
(2,6)
Data
Puts the memory in Power Down mode where power
consumption is reduced to typically less than 1µA
Notes:
1. Command not interpreted in this table will default to read array mode.
2. X = Don’t Care.
3. The first cycle of the RST, RBP or RSIG instruction is followed by read operations to read memory array, Status Register or
Electronic Signature codes. Any number of read cycles can occur after one command cycle.
4. Signature Address bits A0, A1, A6 at V
IL
will output Manufacturer code (20h). Address bits A0 at V
IH
and A1, A6 at V
IL
will output
Device code.
5. Protection Address: A0, A6 at V
IL
, A1 at V
IH
and A16, A17, A18 within the uniform block to be checked, will output the
Block Protection status.
6. Address bits A15-A18 are don’t care for coded address inputs.
7. Optional, additional blocks addresses must be entered within a 80µs delay after last write entry, timeout status can be verified
through DQ3 value. When full command is entered, read Data Polling or Toggle bit until Erase is completed or suspended.
8. Read Data Polling or Toggle bit until Erase completes.
9. A wait time of 5µs is necessary after a Reset command, if the memory is in a Block Erase or Power Down status, before
starting any operation.
10. Writing an RST command to the P/E.C. is mandatory prior to any new operation when the memory is in Power Down mode.
5/31
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