GS8672T36AE-300 datasheet, PDF

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GS8672T36AE-300: DescriptionDDR SRAM, 2MX36, CMOS, PBGA165, 17 X 15 MM, 1 MM PITCH, PLASTIC, BGA-165; Categorystorage storage; File Size1004KB，29 Pages; ManufacturerGSI Technology; Websitehttp://www.gsitechnology.com/

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GS8672T36AE-300 Overview

DDR SRAM, 2MX36, CMOS, PBGA165, 17 X 15 MM, 1 MM PITCH, PLASTIC, BGA-165

GS8672T36AE-300 Parametric

Parameter Name	Attribute value
Maker	GSI Technology
Parts packaging code	BGA
package instruction	LBGA,
Contacts	165
Reach Compliance Code	compliant
ECCN code	3A991.B.2.B
Other features	PIPELINED ARCHITECTURE
JESD-30 code	R-PBGA-B165
length	17 mm
memory density	75497472 bit
Memory IC Type	DDR SRAM
memory width	36
Number of functions	1
Number of terminals	165
word count	2097152 words
character code	2000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	2MX36
Package body material	PLASTIC/EPOXY
encapsulated code	LBGA
Package shape	RECTANGULAR
Package form	GRID ARRAY, LOW PROFILE
Parallel/Serial	SERIAL
Certification status	Not Qualified
Maximum seat height	1.5 mm
Maximum supply voltage (Vsup)	1.9 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
width	15 mm

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Preliminary

GS8672T18/36AE-333/300/250/200

165-Bump BGA

Commercial Temp

Industrial Temp

Features

• On-Chip ECC with virtually zero SER

• Simultaneous Read and Write SigmaDDR™ Interface

• Common I/O bus

• JEDEC-standard pinout and package

• Double Data Rate interface

• Byte Write Capability

• Burst of 2 Read and Write

• 1.8 V +100/–100 mV core power supply

• 1.5 V or 1.8 V HSTL Interface

• Pipelined read operation with self-timed Late Write

• Fully coherent read and write pipelines

• ZQ pin for programmable output drive strength

• IEEE 1149.1 JTAG-compliant Boundary Scan

• Pin-compatible with present 9Mb, 18Mb, 36Mb and 144Mb

devices

• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package

• RoHS-compliant 165-bump BGA package available

72Mb SigmaDDR-II™

Burst of 2 ECCRAM™

Clocking and Addressing Schemes

333 MHz–200 MHz

1.8 V V

1.8 V and 1.5 V

DDQ

The GS8672T18/36AE SigmaDDR-II SRAMs are

synchronous devices. They employ two input register clock

inputs, K and K. K and K are independent single-ended clock

inputs, not differential inputs to a single differential clock input

buffer. The device also allows the user to manipulate the

output register clock inputs quasi independently with the C and

C clock inputs. C and C are also independent single-ended

clock inputs, not differential inputs. If the C clocks are tied

high, the K clocks are routed internally to fire the output

registers instead.

Common I/O x36 and x18 SigmaDDR-II ECCRAMs always

transfer data in two packets. When a new address is loaded, A0

presets an internal 1-bit address counter. The counter

increments by 1 (toggles) for each beat of a burst of two data

transfer.

SigmaDDR™ Family Overview

The GS8672T18/36AE SigmaDDR-II ECCRAMs are built in

compliance with the SigmaDDR-II SRAM pinout standard for

Common I/O synchronous SRAMs. They are 75,497,472-bit

(72Mb) SRAMs. The GS8672T18/36AE SigmaDDR-II

SRAMs are just one element in a family of low power, low

voltage HSTL I/O SRAMs designed to operate at the speeds

needed to implement economical high performance

networking systems.

On-Chip Error Correction Code

GSI's ECCRAMs implement an ECC algorithm that detects

and corrects all single-bit memory errors, including those

induced by Soft Error Rate (SER) events such as cosmic rays,

alpha particles etc. The resulting SER of these devices is

anticipated to be <0.002 FITs/Mb — a 5-order-of-magnitude

improvement over comparable SRAMs with no On-Chip ECC,

which typically have an SER of 200 FITs/Mb or more. SER

quoted above is based on reading taken at sea level.

However, the On-Chip Error Correction (ECC) will be

disabled if a “Half Write” operation is initiated. See the

Byte

Write Contol

section for further information.

Parameter Synopsis

-333

tKHKH

tKHQV

3.0 ns

0.45 ns

-300

3.3 ns

0.45 ns

-250

4.0 ns

0.45 ns

-200

5.0 ns

0.45 ns

Rev: 1.02 5/2010

1/29

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Preliminary

GS8672T18/36AE-333/300/250/200

Background

Common I/O SRAMs, from a system architecture point of view, are attractive in read dominated or block transfer applications.

Therefore, the SigmaDDR-II ECCRAM interface and truth table are optimized for burst reads and writes. Common I/O SRAMs

are unpopular in applications where alternating reads and writes are needed because bus turnaround delays can cut high speed

Common I/O SRAM data bandwidth in half.

Burst Operations

Read and write operations are "burst" operations. In every case where a read or write command is accepted by the ECCRAM, it

will respond by issuing or accepting two beats of data, executing a data transfer on subsequent rising edges of K and K, as

illustrated in the timing diagrams. It is not possible to stop a burst once it starts. Two beats of data are always transferred. This

means that it is possible to load new addresses every K clock cycle. Addresses can be loaded less often, if intervening deselect

cycles are inserted.

Deselect Cycles

Chip Deselect commands are pipelined to the same degree as read commands. This means that if a deselect command is applied to

the ECCRAM on the next cycle after a read command captured by the ECCRAM, the device will complete the two beat read data

transfer and then execute the deselect command, returning the output drivers to high-Z. A high on the LD pin prevents the RAM

from loading read or write command inputs and puts the RAM into deselect mode as soon as it completes all outstanding burst

transfer operations.

SigmaDDR-II ECCRAM Read Cycles

The SRAM executes pipelined reads. The status of the Address, LD and R/W pins are evaluated on the rising edge of K. The read

command (LD low and R/W high) is clocked into the SRAM by a rising edge of K. After the next rising edge of K, the SRAM

produces data out in response to the next rising edge of C (or the next rising edge of K, if C and C are tied high). The second beat

of data is transferred on the next rising edge of C, for a total of two transfers per address load.

SigmaDDR-II ECCRAM Write Cycles

The status of the Address, LD and R/W pins are evaluated on the rising edge of K. The ECCRAM executes "late write" data

transfers. Data in is due at the device inputs on the rising edge of K following the rising edge of K clock used to clock in the write

command (LD and R/W low) and the write address. To complete the remaining beat of the burst of two write transfer, the

ECCRAM captures data in on the next rising edge of K, for a total of two transfers per address load.

Rev: 1.02 5/2010

5/29

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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