UPD70F3204Y datasheet, PDF - EEWORLD Datasheet

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UPD70F3204Y: Description32-BIT SINGLE-CHIP MICROCONTROLLERS; File Size594KB，98 Pages; ManufacturerNEC ( Renesas ); Websitehttps://www2.renesas.cn/zh-cn/

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UPD70F3204Y Overview

32-BIT SINGLE-CHIP MICROCONTROLLERS

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PRELIMINARY PRODUCT INFORMATION

PD703201, 703201Y, 703204, 703204Y,

70F3201, 70F3201Y, 70F3204, 70F3204Y

V850ES/SA2

V850ES/SA3

32-BIT SINGLE-CHIP MICROCONTROLLERS

MOS INTEGRATED CIRCUIT

DESCRIPTION

The

PD703201, 703201Y, 70F3201, and 70F3201Y (V850ES/SA2),

PD703204, 703204Y, 70F3204, and

70F3204Y (V850ES/SA3) are products in the V850 Family

DMA controller.

In addition to their high real-time responsiveness and one-clock-pitch execution of instructions, the V850ES/SA2

and V850ES/SA3 include instructions suited to digital servo control applications such as multiplication instructions

executed via a hardware multiplier, saturation instructions, and bit manipulation instructions. As a real-time control

system, this device provides a high-level cost performance ideal for ultra-low-power DVC and portable audio

applications.

Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before

designing.

V850ES/SA2, V850ES/SA3 User’s Manual Hardware:

To be prepared

V850ES User’s Manual Architecture:

To be prepared

of 32-bit single-chip microcontrollers, and include

peripheral functions such as ROM/RAM, timer/counters, serial interfaces, an A/D converter, a D/A converter, and a

FEATURES

Number of instructions: 83

Minimum instruction execution time:

59 ns (@ 17 MHz operation with main system clock (f

))

74 ns (@ 13.5 MHz operation with main system clock (f

))

General-purpose registers: 32 bits

32 registers

Instruction set:

Signed multiplication, saturation operations, 32-bit

shift instructions, bit manipulation instructions,

load/store instructions

Memory space:

64 MB linear address space

Memory block division function:

2 MB, 2 MB, 4 MB, 8 MB = Total four blocks

External bus interface: 16-bit data bus

Address bus: Separate output enabled

Internal memory

Mask ROM:

256 KB (

PD703201, 703201Y,

703204, 703204Y)

Flash memory: 256 KB (

PD70F3201, 70F3201Y,

70F3204, 70F3204Y)

RAM: 16 KB

The information contained in this document is being issued in advance of the production cycle for the

device. The parameters for the device may change before final production or NEC Corporation, at its own

discretion, may withdraw the device prior to its production.

Not all devices/types available in every country. Please check with local NEC representative for

availability and additional information.

Document No. U15436EJ1V0PM00 (1st edition)

Date Published June 2001 N CP(K)

Printed in Japan

Interrupts and exceptions

Non-maskable interrupts: 2 sources

Maskable interrupts:

38 sources (

PD703201, 70F3201)

39 sources (

PD703201Y, 70F3201Y)

39 sources (

PD703204, 70F3204)

40 sources (

PD703204Y, 70F3204Y)

Software exceptions: 32 sources

Exception trap: 1 source

I/O lines Total: 82 (V850ES/SA2)

102 (V850ES/SA3)

Timer/counters

16-bit timer: 2 channels

8-bit timer: 4 channels

Real-time counter (for watch): 1 channel

Watchdog timer: 1 channel

2001

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