WEDPN8M64V-XB2X
8Mx64 Synchronous DRAM
FEATURES
High Frequency = 100, 125, 133MHz
Package:
• 219 Plastic Ball Grid Array (PBGA), 21 x 21mm
Single 3.3V ±0.3V power supply
Unbuffered
Fully synchronous; all signals registered on positive edge of
system clock cycle
Internal pipelined operation; column address can be
changed every clock cycle
Internal banks for hiding row access/precharge
Programmable Burst length 1,2,4,8 or full page
4,096 refresh cycles
Commercial, Industrial and Military Temperature Ranges
Organized as 8M x 64
• User Configurable as 2 x 8M x 32 or
4 x 8M x 16
Weight: WEDPN8M64V-XB2X - 2 grams typical
GENERAL DESCRIPTION
The 64MByte (512Mb) SDRAM is a high-speed CMOS, dynamic
random-access memory using 4 chips containing 134,217,728 bits.
Each chip is internally configured as a quad-bank DRAM with a
synchronous interface. Each of the chip’s 33,554,432-bit banks is
organized as 4,096 rows by 512 columns by 16 bits.
Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for a programmed
number of locations in a programmed sequence. Accesses begin
with the registration of an ACTIVE command, which is then followed
by a READ or WRITE command. The address bits registered
coincident with the ACTIVE command are used to select the bank
and row to be accessed (BA0, BA1 select the bank; A0-11 select
the row). The address bits registered coincident with the READ or
WRITE command are used to select the starting column location
for the burst access.
The SDRAM provides for programmable READ or WRITE burst
lengths of 1, 2, 4 or 8 locations, or the full page, with a burst
terminate option. An AUTO PRECHARGE function may be enabled
to provide a self-timed row precharge that is initiated at the end
of the burst sequence.
The 512Mb SDRAM uses an internal pipelined architecture to
achieve high-speed operation. This architecture is compatible with
the 2n rule of prefetch architectures, but it also allows the column
address to be changed on every clock cycle to achieve a high-
speed, fully random access. Precharging one bank while accessing
one of the other three banks will hide the precharge cycles and
provide seamless, high-speed, random-access operation.
The 512Mb SDRAM is designed to operate in 3.3V, low-power
memory systems. An auto refresh mode is provided, along with a
power-saving, power-down mode.
All inputs and outputs are LVTTL compatible. SDRAMs offer
substantial advances in DRAM operating performance, including
continued on page 4
BENEFITS
58% SPACE SAVINGS
Reduced part count
Reduced trace lengths for lower parasitic capacitance
Laminate interposer for optimum TCE match
Suitable for hi-reliability applications
Upgradeable to 16M x 64 density (WEDPN16M64V-XB2X)
* This product is subject to change without notice.
DENSITY COMPARISONS
Discrete Approach (mm)
11.9
11.9
11.9
11.9
WEDPN8M64V-XB2X
22.3
54
TSOP
54
TSOP
54
TSOP
54
TSOP
WEDPN8M64V-XB2X
21
21
S
A
V
I
N
G
S
58%
Area
4 x 265mm
2
= 1,060mm
2
441mm
2
Microsemi Corporation reserves the right to change products or specifications without notice.
July 2011
Rev. 3
© 2011 Microsemi Corporation. All rights reserved.
1
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WEDPN8M64V-XB2X
FIGURE 1 – PIN CONFIGURATION
Top View
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
DQ
1
DQ
3
DQ
6
DQ
7
CAS
0
#
CS
0
#
V
SS
V
SS
Vss
Vss
DQ
56
DQ
57
DQ
60
DQ
62
Vss
2
DQ
0
DQ
2
DQ
4
DQ
5
DQML0
3
DQ
14
DQ
12
DQ
10
DQ
8
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
DQ
55
DQ
53
DQ
51
DQ
49
4
DQ
15
DQ
13
DQ
11
DQ
9
DQMH0
5
V
SS
V
SS
V
CC
V
CC
Vss
Vss
Vss
V
SS
V
SS
Vss
6
V
SS
V
SS
V
CC
V
CC
Vss
7
A
9
A
0
A
2
DNU
NC
8
A
10
A
7
A
5
DNU
BA
0
9 10
A
11
A
6
A
4
DNU
BA
1
A
8
A
1
A
3
DNU
NC
11 12
V
CC
V
CC
V
SS
V
SS
Vss
V
CC
V
CC
V
SS
V
SS
Vss
RAS
1
#
CAS
1
#
V
CC
V
CC
Vcc
Vcc
13 14
DQ
16
DQ
18
DQ
20
DQ
22
DQML1
15 16
DQ
31
DQ
29
DQ
27
DQ
26
Vss
DQMH1
DQ
17
DQ
19
DQ
21
DQ
23
V
SS
V
SS
V
SS
Vss
V
SS
V
SS
V
SS
V
SS
DQ
40
DQ
42
DQ
44
DQ
46
V
SS
DQ
30
DQ
28
DQ
25
DQ
24
CLK
1
CKE
1
V
CC
V
CC
CS
2
#
CAS
2
#
DQ
39
DQ
38
DQ
35
DQ
33
V
CC
WE
0
#
RAS
0
#
V
SS
V
SS
CKE
3
CLK
3
DQMH3
CLK
0
CKE
0
V
CC
V
CC
CS
3
#
WE
1
#
CS
1
#
V
SS
V
SS
CKE
2
CLK
2
DQMH2
Vcc
V
CC
V
CC
RAS
2
#
WE
2
#
DQML2
CAS
3
#
RAS
3
#
WE
3
#
DQ
54
DQ
52
DQ
50
DQ
48
DQML3
Vcc
Vcc
V
SS
V
CC
V
CC
Vcc
Vcc
Vcc
Vss
Vss
Vcc
Vcc
Vcc
Vss
Vss
Vss
Vss
Vss
Vcc
Vcc
Vss
Vss
Vss
Vcc
Vcc
Vss
Vss
V
CC
V
SS
V
SS
Vss
Vss
V
CC
V
SS
V
SS
DQ
58
DQ
59
DQ
61
DQ
63
Vcc
V
SS
V
CC
V
CC
DQ
41
DQ
43
DQ
45
DQ
47
DQ
37
DQ
36
DQ
34
DQ
32
NOTE: DNU = Do Not Use; to be left unconnected for future upgrades.
NC = Not Connected Internally.
Microsemi Corporation reserves the right to change products or specifications without notice.
July 2011
Rev. 3
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WEDPN8M64V-XB2X
FIGURE. 2 – FUNCTIONAL BLOCK DIAGRAM
WE
0
#
RAS
0
#
CAS
0
#
WE# RAS# CAS#
A
0-11
BA
0-1
CLK
0
CKE
0
CS
0
#
DQML
0
DQMH
0
A
0-11
BA
0-1
DQ
0
DQ
0
•
8M x 16
•
CLK
•
U0
CKE
•
CS#
•
DQML
•
DQMH
DQ
15
•
•
•
•
•
•
DQ
15
WE
1
#
RAS
1
#
CAS
1
#
WE# RAS# CAS#
A
0-11
BA
0-1
DQ
0
DQ
16
CLK
1
CKE
1
CS
1
#
DQML
1
DQMH
1
•
8M x 16
•
CLK
•
U1
CKE
•
CS#
•
•
DQML
DQMH
DQ
15
•
•
•
•
•
•
DQ
31
WE
2
#
RAS
2
#
CAS
2
#
WE# RAS# CAS#
A
0-11
BA
0-1
DQ
0
DQ
32
CLK
2
CKE
2
CS
2
#
DQML
2
DQMH
2
•
8M x 16
•
CLK
•
U2
CKE
•
CS#
•
•
DQML
DQMH
DQ
15
•
•
•
•
•
•
DQ
47
WE
3
#
RAS
3
#
CAS
3
#
WE# RAS# CAS#
A
0-11
BA
0-1
DQ
0
DQ
48
CLK
3
CKE
3
CS
3
#
DQML
3
DQMH
3
•
8M x 16
•
CLK
•
U3
CKE
•
CS#
•
•
DQML
DQMH
DQ
15
•
•
•
•
•
•
DQ
63
Microsemi Corporation reserves the right to change products or specifications without notice.
July 2011
Rev. 3
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WEDPN8M64V-XB2X
the ability to synchronously burst data at a high data rate with
automatic column-address generation, the ability to interleave
between internal banks in order to hide precharge time and the
capability to randomly change column addresses on each clock
cycle during a burst access.
The Mode Register must be loaded when all banks are idle, and
the controller must wait the specified time before initiating the
subsequent operation. Violating either of these requirements will
result in unspecified operation.
FIGURE 3 – MODE REGISTER DEFINITION
FUNCTIONAL DESCRIPTION
Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for a
programmed number of locations in a programmed sequence.
Accesses begin with the registration of an ACTIVE command which
is then followed by a READ or WRITE command. The address bits
registered coincident with the ACTIVE command are used to select
the bank and row to be accessed (BA
0
and BA
1
select the bank,
A
0-11
select the row). The address bits (A
0-8
) registered coincident
with the READ or WRITE command are used to select the starting
column location for the burst access.
Prior to normal operation, the SDRAM must be initialized. The following
sections provide detailed information covering device initialization,
register definition, command descriptions and device operation.
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
Address Bus
Mode Register (Mx)
Reserved* WB Op Mode CAS Latency
BT
Burst Length
*Should program
M11, M10 = 0, 0
to ensure compatibility
with future devices.
M2 M1M0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
1
2
4
8
Burst Length
M3 = 0
M3 = 1
1
2
4
8
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Full Page
INITIALIZATION
SDRAMs must be powered up and initialized in a predefined
manner. Operational procedures other than those specified may
result in undefined operation. Once power is applied and the clock
is stable (stable clock is defined as a signal cycling within timing
constraints specified for the clock pin), the SDRAM requires a
100μs delay prior to issuing any command other than a COMMAND
INHIBIT or a NOP. Starting at some point during this 100μs period
and continuing at least through the end of this period, COMMAND
INHIBIT or NOP commands should be applied.
Once the 100μs delay has been satisfied with at least one
COMMAND INHIBIT or NOP command having been applied, a
PRECHARGE command should be applied. All banks must be
precharged, thereby placing the device in the all banks idle state.
Once in the idle state, two AUTO REFRESH cycles must be
performed. After the AUTO REFRESH cycles are complete, the
SDRAM is ready for Mode Register programming. Because the
Mode Register will power up in an unknown state, it should be
loaded prior to applying any operational command.
M8
0
-
M7
0
-
M3
0
1
Burst Type
Sequential
Interleaved
M6 M5 M4
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
CAS Latency
Reserved
Reserved
2
3
Reserved
Reserved
Reserved
Reserved
M6-M0
Defined
-
Operating Mode
Standard Operation
All other states reserved
M9
0
1
Write Burst Mode
Programmed Burst Length
Single Location Access
REGISTER DEFINITION
MODE REGISTER
The Mode Register is used to define the specific mode of operation
of the SDRAM. This definition includes the selec-tion of a burst
length, a burst type, a CAS latency, an operating mode and a
write burst mode, as shown in Figure 3. The Mode Register is
programmed via the LOAD MODE REGISTER command and will
retain the stored information until it is programmed again or the
device loses power.
Mode register bits M0-M2 specify the burst length, M3 specifies the
type of burst (sequential or interleaved), M4-M6 specify the CAS
latency, M7 and M8 specify the operating mode, M9 specifies the
WRITE burst mode, and M10 and M11 are reserved for future use.
Microsemi Corporation reserves the right to change products or specifications without notice.
July 2011
Rev. 3
© 2011 Microsemi Corporation. All rights reserved.
4
BURST LENGTH
Read and write accesses to the SDRAM are burst oriented, with
the burst length being programmable, as shown in Figure 3. The
burst length determines the maximum number of column locations
that can be accessed for a given READ or WRITE command.
Burst lengths of 1, 2, 4 or 8 locations are available for both the
sequential and the interleaved burst types, and a full-page burst
is available for the sequential type. The full-page burst is used in
conjunction with the BURST TERMINATE command to generate
arbitrary burst lengths.
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WEDPN8M64V-XB2X
Reserved states should not be used, as unknown operation or
incompatibility with future versions may result.
When a READ or WRITE command is issued, a block of columns
equal to the burst length is effectively selected. All accesses for that
burst take place within this block, meaning that the burst will wrap
within the block if a boundary is reached. The block is uniquely
selected by A
1-8
when the burst length is set to two; by A
2-8
when
the burst length is set to four; and by A
3-8
when the burst length
is set to eight. The remaining (least significant) address bit(s) is
(are) used to select the starting location within the block. Full-page
bursts wrap within the page if the boundary is reached.
CAS LATENCY
The CAS latency is the delay, in clock cycles, between the
registration of a READ command and the availability of the
fi
rst
piece of output data. The latency can be set to two or three clocks.
If a READ command is registered at clock edge n, and the latency
is m clocks, the data will be available by clock edge n+m. The I/
Os will start driving as a result of the clock edge one cycle earlier
(n + m - 1), and provided that the relevant access times are met,
the data will be valid by clock edge n + m. For example, assuming
that the clock cycle time is such that all relevant access times are
met, if a READ command is registered at T0 and the latency is
programmed to two clocks, the I/Os will start driving after T1 and
the data will be valid by T2. Table 2 below indicates the operating
frequencies at which each CAS latency setting can be used.
Reserved states should not be used as unknown operation or
incompatibility with future versions may result.
BURST TYPE
Accesses within a given burst may be programmed to be either
sequential or interleaved; this is referred to as the burst type and
is selected via bit M3.
The ordering of accesses within a burst is determined by the burst
length, the burst type and the starting column address, as shown
in Table 1.
TABLE 2 – CAS LATENCY
ALLOWABLE OPERATING
FREQUENCY (MHz)
SPEED
-100
-125
-133
CAS
LATENCY = 2
75
100
100
CAS
LATENCY = 3
100
125
133
TABLE 1 – BURST DEFINITION
Burst
Length
2
A1
0
0
1
1
A1
0
0
1
1
0
0
1
1
n = A
0-9/8/7
(location 0-y)
Starting Column
Address
A0
0
1
A0
0
1
0
1
A0
0
1
0
1
0
1
0
1
Order of Accesses Within a Burst
Type = Sequential
Type = Interleaved
0-1
1-0
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
Cn, Cn + 1, Cn + 2
Cn + 3, Cn + 4...
…Cn - 1,
Cn…
0-1
1-0
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
Not Supported
4
OPERATING MODE
The normal operating mode is selected by setting M7and M8 to zero;
the other combinations of values for M7 and M8 are reserved for future
use and/or test modes. The programmed burst length applies to both
READ and WRITE bursts.
Test modes and reserved states should not be used because
unknown operation or incompatibility with future versions may
result.
8
A2
0
0
0
0
1
1
1
1
WRITE BURST MODE
When M9 = 0, the burst length programmed via M0-M2 applies
to both READ and WRITE bursts; when M9 = 1, the programmed
burst length applies to READ bursts, but write accesses are single-
location (nonburst) accesses.
Full
Page
(y)
NOTES:
1. For full-page accesses: y = 512.
2. For a burst length of two, A
1-8
select the block-of-two burst; A0 selects the starting column within
the block.
3. For a burst length of four, A
2-8
select the block-of-four burst; A0-1 select the starting column
within the block.
4. For a burst length of eight, A
3-8
select the block-of-eight burst; A
0-2
select the starting column
within the block.
5. For a full-page burst, the full row is selected and A
0-8
select the starting column.
6. Whenever a boundary of the block is reached within a given sequence above, the following
access wraps within the block.
7. For a burst length of one, A
0-8
select the unique column to be accessed, and Mode Register bit
M3 is ignored.
COMMANDS
The Truth Table provides a quick reference of available commands.
This is followed by a written description of each command. Three
additional Truth Tables appear following the Operation section;
these tables provide current state/next state information.
COMMAND INHIBIT
The COMMAND INHIBIT function prevents new commands from
being executed by the SDRAM, regardless of whether the CLK
signal is enabled. The SDRAM is effectively deselected. Operations
already in progress are not affected.
Microsemi Corporation reserves the right to change products or specifications without notice.
July 2011
Rev. 3
© 2011 Microsemi Corporation. All rights reserved.
5
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