SYS816000RKX - 70/85/10
Issue 1.0 : March 1999
Description
The SYS816000 is an industry standard plastic
128Mbit Static RAM Module housed in a 40 pin plastic
Single-in-line package organised as 16M x 8, with
access times of 70/85 and 100ns. The module utilizes
state of the art packaging technology to give a height
of only 0.8" and maximum thickness 0.16". The
SYS816000 offers the highest density SRAM available
without resorting to expensive 3D technologies.
The module provides full buffering of address, data
paths and all control signals so that the system only
needs to drive one or two loads. The memory content
is provided by 32 pieces of 4Mbit SRAM. operating at
3 volts. The SYS816000 has battery backup capability
at 2 volt operation.
The SYS816000 has the same pin definition as the
SYS88000RKX and SYS84000RKX with the addition of
an extra pin on either end.
Features
Access Times of 70/85/100 ns
Very simple operation
40 Pin SIP package
3 Volt Supply ± 10%
Low Power Dissipation:
Average (min cycle) 150 mW
Standby
2.25 mW
• Completely Static Operation
• On-board Supply Decoupling Capacitors
•
•
•
•
•
Block Diagram
Address
/CS
/WE
A0
A23
Buffer and Decode Logic
/OE
4Mb
SRAM
0
Control
31
Pin Functions
D0
D7
Data
Description
Address Inputs
Data Input/Output
Chip Select
Write Enable
Output Enable
No Connect
Power (+3V)
Ground
Signal
A0 - A23
D0 - D7
/CS
/WE
/OE
NC
Vcc
Gnd
1
2
3
4
5
A23
A22
A20
Vcc
/WE
D2
D3
D0
A1
A2
11
12
13
14
15
16
17
18
19
20
A3
A4
Gnd
D5
A10
A11
A5
A13
A14
A19
21
22
23
24
25
26
27
28
29
30
/CS
A15
A16
A12
A18
A6
D1
Gnd
A0
A7
31
32
33
34
35
36
37
38
39
40
A8
A9
D7
D4
D6
A17
Vcc
/OE
A21
NC
Pin
Signal
Pin
Signal Pin
Signal
Pin
Signal
Pin Definition
Package Details
Plastic 40 Pin Single-in-line (SIP)
Dimensions 4.05" x 0.8" x 0.16"
6
7
8
9
10
11,403 West Bernardo Court, San Diego, CA 92127 Tel (619) 674 2233 Fax (619) 674 2230
16M X 8 SRAM MODULE
SYS816000 - 70/85/10
Issue 1.0 : March 1999
DC Operating Conditions
Absolute Maximum Ratings
(1)
Parameter
Voltage on any pin relative to V
SS
Power Dissipation
Storage Temperature
Symbol
V
T(2)
Min
-0.5
-
-65
Typ
-
-
-
Max
Vcc+0.5
1.5
150
Units
V
W
o
P
T
T
STG
C
Notes : (1)
Stresses above those listed may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at those or any other conditions above those indi-
cated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
V
T
can be -2.0V pulse of less than 10ns.
(2)
Recommended Operating Conditions
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Operating Temperature
Commercial
Industrial
Symbol
V
CC
V
IH
V
IL
T
A
T
AI
Min
2.7
2.2
-0.3
0
-40
Typ
3.0
-
-
-
-
Max
3.3
V
CC
+0.3
0.6
70
85
Unit
V
V
V
o
o
C
C
DC Electrical Characteristics
(V
CC
=3V±10%) T
A
0 to 70
o
C
Parameter
I/P Leakage Current Address,OE,WE
Output Leakage Current (Worst Case)
Average Supply Current (100% duty)
Standby Supply Current
TTL
CMOS
Output Voltage
Symbol
I
LI
I
LO
I
CC1
I
SB1
I
SB2
V
OL
V
OH
Test Condition
0V
<
V
IN
<
V
CC
CS = V
IH,
V
I/O
= GND to V
CC
Min Cycle, CS = V
IL
,V
IL
<V
IN
<V
IH
CS = V
IH
CS
>
V
CC
-0.2V, 0.2<V
IN
<V
CC
-0.2V
I
OL
= 8.0mA
I
OH
= -4.0mA
Min
-36
-36
-
-
-
-
2.4
Typ
-
-
-
-
-
-
-
Max
36
36
48
10
750
0.4
-
Unit
µA
µA
mA
mA
µA
V
V
Typical values are at V
CC
= 3.0V,T
A
= 25
o
C and specified loading.
Page 2
Issue 1.0 : March 1999
SYS816000 - 70/85/10
Capacitance
(V
CC
=3V±10%,T
A
=25
o
C)
Parameter
Input Capacitance
(Addresses A0-A17,/WE)
Input Capacitance (
/CS)
Input Capacitance
(other)
I/O Capacitance (
Data D0-D7)
Symbol
Test Condition
Max
Unit
C
IN1
C
IN2
C
IN3
C
I/O
V
IN
= 0V
V
IN
= 0V
V
IN
= 0V
V
I/O
= 0V
8
24
16
8
pF
pF
pF
pF
Note: Capacitance calculated, not measured
AC Test Conditions
Notes: (1)
(2)
(3)
(4)
(5)
Input pulse levels: 0.4V to 2.2V
Input rise and fall times: 5ns
Input and Output timing reference levels: 1.5V
Output load: see diagram
V
CC
= 3V±10%
I/O Pin
645
Ω
1.76V
100pF
Operation Truth Table
/CS
H
L
L
L
L
/OE
X
L
H
L
H
/WE
X
H
L
L
H
Data Pins
High Impedance
Data Out
Data In
Invalid State
High-Impedance
Supply Current
I
SB1
, I
SB2
I
CC1
I
CC1
I
CC1
I
SB1
, I
SB2
Mode
Standby
Read
Write
Invalid
High-Z
Notes
H = V
IH
: L =V
IL
: X = V
IH
or V
IL
Page 3
SYS816000 - 70/85/10
Issue 1.0 : March 1999
AC Operating Conditions
Read Cycle
70ns
Parameter
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Enable to Output Valid
Output Hold from Address Change
Chip Selection to Output in Low Z
Output Enable to Output in Low Z
Chip Deselection to O/P in High Z
Output Disable to Output in High Z
Symbol
t
RC
t
AA
t
ACS
t
OE
t
OH
t
CLZ
t
OLZ
t
CHZ
t
OHZ
Min
70
-
-
-
10
10
5
0
0
Max
-
70
70
35
-
-
-
25
25
85ns
Min
85
-
-
-
10
10
5
0
0
Max
-
85
85
40
-
-
-
25
25
100ns
Min
100
-
-
-
15
10
5
0
0
Max
-
100
100
50
-
-
-
30
30
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Timing Waveform
(1,2)
t
RC
Address
t
AA
/OE
t
OE
/CS
t
CLZ
Dout
AC Read Characteristics
Notes (1)
(2)
(3)
(4)
(5)
Page 4
t
OH
t
OLZ
t
ACS
(4,5)
t
OHZ
Data Valid
(3)
Don't
care
t
CHZ(3,4,5)
/WE is High for Read Cycle.
All read cycle timing is referenced from the last valid address to the first transition address.
t
CHZ
and t
OHZ
are defined as the time at which the outputs achieve open circuit conditions and
are not referenced to output voltage levels.
At any given temperature and voltage condition, t
CHZ
(max) is less than t
CLZ
(min) both for a
given moduleand from module to module.
These parameters are sampled and not 100% tested.
Issue 1.0 : March 1999
SYS816000 - 70/85/10
Write Cycle
70ns
Parameter
Write Cycle Time
Chip Selection to End of Write
Address Valid to End of Write
Address Setup Time
Write Pulse Width
Write Recovery Time
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output active from End of Write
Symbol
t
WC
t
CW
t
AW
t
AS
t
WP
t
WR
t
WHZ
t
DW
t
DH
t
OW
Min
70
60
60
0
55
0
0
30
0
5
Max
-
-
-
-
-
-
25
-
-
-
85ns
Min
85
70
70
0
55
0
0
35
0
5
Max
-
-
-
-
-
-
25
-
-
-
100ns
Min
100
80
80
0
70
0
0
40
0
5
Max
-
-
-
-
-
-
30
-
-
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Cycle No.1 Timing Waveform
(1,4)
t
WC
Address
t
WR(7)
/OE
t
AS(6)
t
AW
t
CW
Don't
Care
/CS
/WE
t
OHZ(3,9)
Dout
Din
High-Z
t
WP(2)
High-Z
t
DW
t
DH
t
OW
(8)
Data Valid
Page 5
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