Cover
88F5281
Feroceon
®
SoC
Datasheet
Doc. No. MV-S103889-00, Rev. E
April 29, 2008, Preliminary
Marvell.
Moving Forward Faster
Document Classification: Proprietary Information
88F5281
Datasheet
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Doc. No. MV-S103889-00 Rev. E
Page 2
Document Classification: Proprietary Information
Copyright © 2008 Marvell
April 29, 2008, Preliminary
88F5281
Feroceon
®
SoC
Datasheet
PRODUCT OVERVIEW
The Marvell
®
88F5281 device is a high-performance
integrated controller. It is based on the Marvell
Feroceon
®
CPU core, which is compliant with the
ARMv5TE. The device is intended for use in a wide
range of systems with extensive communication and
connectivity requirements.
•
Supports DSP instructions to boost performance
•
•
•
•
•
•
•
•
•
•
for signal processing applications
Includes MMU to support virtual memory features
MPU can be used instead when not using MMU
32-KByte I-Cache and 32-KByte D-Cache
64-bit internal data bus
Variable pipeline stages—six to nine stages
Out-of-order execution for increased performance
In-order retire via a Reordering Buffer (ROB)
Branch Prediction Unit
Supports JTAG/ARM-compatible ICE
Supports both Big and Little Endian modes
FEATURES
High performance integrated controller
•
High performance Feroceon 88FR531-vd dual
issue CPU with Vector Floating Point (VFP) support
•
High bandwidth dual-port memory controller
(16-/32-bit DDR1/DDR2 SDRAM)
•
Single PCI Express (x1) port with integrated PHY
•
Single 64-bit PCI2.2/PCI-X 133 MHz port
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Single Gigabit Ethernet MAC (10/100/1000 Mbps)
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Single USB2.0 peripheral or host port with
integrated PHY
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Two-Wire Serial Interface (TWSI)
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2 UART ports
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32-bit device bus with up to 4 chip selects
•
NAND Flash support
•
Integrated DMA engine (4 channels)
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20 multi-purpose pins
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Interrupt controller
•
Timers
Feroceon 88FR531-vd dual issue CPU with VFP
support
•
Up to 500 MHz
•
Super scalar, dual issue CPU
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Single precision and double precision VFP support
•
32-bit and 16-bit RISC architecture
•
Compliant with v5TE architecture, published in the
ARM Architecture Reference Manual,
Second
Edition
•
Supports 32-bit instruction set for performance and
flexibility
•
Supports 16-bit Thumb instruction set for code
density
DDR1/DDR2 SDRAM controller
•
DDR SDRAM with a clock ratio of 1:2 or 1:3
between the DDR SDRAM and the Feroceon core,
respectively
•
16-bit/32-bit interface
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DDR1 at up to 166 MHz
•
DDR2 at up to 200 MHz
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Supports up to two dual sided DIMMs
•
Supports DDR components of x8 and x16
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Dual channel memory controller
Reduced CPU to DDR SDRAM latency
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SSTL 2.5V I/Os in DDR1, 1.8V I/Os in DDR2
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Supports four DDR SDRAM banks (CSs)
•
DDR1 supports device densities of 128, 256, and
512 Mb
•
DDR2 supports device densities of 256 and
512 Mb
•
Up to 1 GB (32-bit interface) and 0.5 GB (16-bit
interface) total memory space
•
Supports DDR SDRAM bank interleaving between
all DDR SDRAM banks (both the physical banks
and the four internal banks of the DDR SDRAM
devices)
•
Supports up to 16 open pages (page per bank)
•
Supports configurable DDR SDRAM timing
parameters
•
Supports up to 32-byte burst per single DDR
SDRAM access
•
Single ended DQS in DDR2
•
DDR1/DDR2 pad auto calibration
•
Supports DDR2 On Die Termination (ODT)
Copyright © 2008 Marvell
April 29, 2008, Preliminary
Document Classification: Proprietary Information
Doc. No. MV-S103889-00 Rev. E
Page 3
88F5281
Datasheet
PCI Express interface (x1)
•
PCI Express Base 1.0a compatible
•
Integrated low power SERDES PHY, based on
Marvell SERDES technology
•
Root Complex Port
•
Can also be configured as an Endpoint port
•
x1 link width
•
2.5 GHz signalling
•
Lane polarity reversal support
•
Maximum payload size of 128 bytes
•
Single Virtual Channel (VC-0)
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Replay buffer support
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Extended PCI Express configuration space
•
Advanced Error Reporting (AER) support
•
Power management: L0s and SW L1 support
•
Interrupt emulation message support
•
Error message support
PCI Express master specific features
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Single outstanding read transaction
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Maximum read request of up to 128 bytes
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Maximum write request of up to 128 bytes
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Up to four outstanding read transactions in
Endpoint mode
PCI Express target specific features
•
Supports up to eight read request transactions
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Maximum read request size of 4 KB
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Maximum write request of 128 bytes
•
Supports PCI Express access to all of the device’s
internal registers
64-bit PCI/PCI-X Interface
•
66 MHz PCI 2.2 compliant interface
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133 MHz PCI-X compliant interface
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3.3V I/Os, 5V tolerant
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Supports 64-bit addressing via DAC transactions
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Configurable PCI arbiter for up to six masters
PCI/PCI-X master specific features
•
Supports all PCI and PCI-X cycles
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Host to PCI bridge—translates CPU cycles to PCI
Memory, I/O, or configuration cycles
•
Supports DMA bursts between PCI and memory
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Supports transaction combining to unlimited PCI
burst (conventional PCI)
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Supports up to four outstanding split transactions
(PCI-X)
PCI/PCI-X target specific features
•
Supports all PCI and PCI-X cycles
•
Supports programmable aggressive read prefetch
(conventional PCI)
•
Supports up to 4 KB read per single transaction
•
•
•
•
•
(PCI-X)
Supports unlimited burst write with zero wait states
Supports up to four delayed reads (conventional
PCI)
Supports up to four split reads (PCI-X)
Supports PCI access to all of the device’s internal
registers
PCI address remapping to local memory
PICMG Compact PCI Hot-Swap ready
PCI/PCI-X “Plug and Play” support
•
Plug and Play compatible configuration registers
•
PCI configuration registers that are accessible from
both the Feroceon CPU core and PCI
•
Vital Product Data (VPD) support
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PCI Power Management (PMG) support
•
Message Signal Interrupts (MSI) support
Integrated Single GbE (10/100/1000) MAC
•
Supports 10/100/1000 Mbps
•
MII, GMII or RGMII Interface
•
Proprietary 200 Mbps Marvell MII (MMII) interface
•
Dedicated DMA for data movement between
memory and port
•
Priority Queuing on receive based on DA, VLAN
Tag, and IP TOS
•
Layer 2/3/4 frame encapsulation detection
•
TCP/IP checksum on receive and transmit
•
DA address filtering
USB2.0 Peripheral or Host port
•
USB 2.0 compliant
•
Integrated USB 2.0 PHY
•
EHCI compatible as a host
•
As a host, supports direct connection to all
peripheral types (LS, FS, HS)
•
As a peripheral, connects to all host types (HS, FS)
and hubs
•
Up to 4 independent endpoints supporting control,
interrupt, bulk, and isochronous data transfers
•
Dedicated DMA for data movement between
memory and port
Two-Wire Serial Interface (TWSI)
•
Master/slave operation
•
Serial ROM initialization
Two UART interfaces
•
16550 UART compatible
•
Two pins for transmit and receive operations
•
Two pins for modem control functions
Doc. No. MV-S103889-00 Rev. E
Page 4
Document Classification: Proprietary Information
Copyright © 2008 Marvell
April 29, 2008, Preliminary
Features
Device Bus Controller
•
8-/16-/32-bit width
•
166 MHz clock frequency
•
3.3V I/Os
•
Supports many types of standard memory devices
such as FLASH, ROM, and SyncBurst SRAM
•
Four chip selects with programmable timing
•
Optional external wait-state support
•
Boot ROM support
NAND Flash support
•
Glueless interface to CE don’t care NAND Flash
through the device bus interface
•
Glueless interface to CE care NAND Flash through
the device bus and MPP interfaces
•
Boot from NAND Flash when the 1st block, placed
on 00h block address, is guaranteed to be a valid
block with no errors
•
Supports read bursts of up to 128 bytes
Four channel Independent DMA controller
•
Chaining via linked-lists of descriptors
•
Moves data from any to any interface
•
Supports increment or hold on both source and
destination address
20 multi-purpose pins dedicated for peripheral
functions and general purpose I/O
•
Each pin can be configured independently
•
GPIO inputs can be used to register interrupts from
external devices and to generate maskable
interrupts
Interrupt controller
•
Maskable interrupts to Feroceon core
•
In endpoint mode, maskable interrupts to PCI/PCI
Express interfaces
Timers
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Two general purpose 32-bit timer/counters
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One 32-bit Watchdog timer
Internal Architecture
•
Mbus-L bus for high-performance, low latency
Feroceon CPU core to DDR SDRAM connectivity
•
Advanced Mbus (crossbar extension) architecture
with any to any concurrent IO connectivity
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Dual port DDR SDRAM controller connectivity to
both CPU and Mbus
Bootable from:
•
Device interface, including glueless boot from
NAND flash
•
PCI Express interface
•
PCI interface
HSBGA, 23x23 mm, 426-pin package,
1 mm ball pitch
Copyright © 2008 Marvell
April 29, 2008, Preliminary
Document Classification: Proprietary Information
Doc. No. MV-S103889-00 Rev. E
Page 5
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