Product Specification
PE4308
Product Description
The PE4308 is a high linearity, 5-bit RF Digital Step Attenuator
(DSA) covering 31 dB attenuation range in 1dB steps, and is
pin compatible with the PE430x series. This 75-ohm RF DSA
provides both parallel (latched or direct mode) and serial
CMOS control interface, operates on a single 3-volt supply and
maintains high attenuation accuracy over frequency and
temperature. It also has a unique control interface that allows
the user to select an initial attenuation state at power-up. The
PE4308 exhibits very low insertion loss and low power
consumption. This functionality is delivered in a 4x4 mm QFN
footprint.
The PE4308 is manufactured on Peregrine’s UltraCMOS™
process, a patented variation of silicon-on-insulator (SOI)
technology on a sapphire substrate, offering the performance
of GaAs with the economy and integration of conventional
CMOS.
Figure 1. Functional Schematic Diagram
75 Ω RF Digital Attenuator
5-bit, 31 dB, DC – 4.0 GHz
Features
Attenuation: 1 dB steps to 31 dB
Flexible parallel and serial programming
interfaces
Latched or direct mode
Unique power-up state selection
Positive CMOS control logic
High attenuation accuracy and linearity
over temperature and frequency
Very low power consumption
Single-supply operation
75 Ω impedance
Pin compatible with PE430x series
Packaged in a 20 Lead 4x4 mm QFN
Switched Attenuator Array
RF Input
Parallel Control
Serial Control
Power-Up Control
5
Table 1. Electrical Specifications @ +25°C, V
DD
= 3.0 V
Parameter
Insertion Loss
2
BS
C
3
Control Logic Interface
2
Test Conditions
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Frequency
Minimum
DC
-
-
30
-
10
-
O
E
DC ≤1.2 GHz
DC ≤1.2 GHz
Any Bit or Bit
Combination
1 MHz ≤1.2 GHz
1 MHz ≤1.2 GHz
DC ≤1.2 GHz
Two-tone inputs up to
+18 dBm
50% control to 0.5 dB
of final value
LE
PE
T
20 Lead 4x4 mm QFN
Figure 2. Package Type
RF Output
Typical
1.4
-
34
52
13
-
43
2000
1.95
-
-
-
1
E
14
Maximum
±(0.2 + 4% of atten setting)
Not to Exceed +0.4 dB
Units
MHz
dB
dB
dB
dBm
dBm
dB
s
1 dB Compression3,4
Input IP3
1,2,4
Return Loss
Switching Speed
Notes: 1.
2.
3.
4.
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Attenuation Accuracy
Operation Frequency
Device Linearity will begin to degrade below 1 MHz
See figures on Pages 4 to 6 for data across frequency.
Note Absolute Maximum in Table 3.
Measured in a 50 Ω system.
©2003-2006 Peregrine Semiconductor Corp. All rights reserved.
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PE4308
Product Specification
Figure 14. Pin Configuration (Top View)
GND
N/C
C1
C2
C4
Table 3. Absolute Maximum Ratings
Symbol
V
DD
V
I
Parameter/Conditions
Power supply voltage
Voltage on any input
Storage temperature range
Input power (50Ω)
ESD voltage (Human Body
Model)
Min
-0.3
-0.3
-65
Max
4.0
V
DD
+
0.3
150
+30
500
Units
V
V
°C
dBm
V
20
19
18
17
C16
RF1
Data
Clock
LE
16
1
2
3
4
5
15
C8
RF2
P/S
Vss/GND
GND
20-lead
QFN
4x4mm
Exposed Solder Pad
T
ST
P
IN
V
ESD
14
13
12
11
Table 4. Operating Ranges
Parameter
V
DD
Power Supply
Voltage
E
14
Min
2.7
10
6
7
8
9
Typ
3.0
Max
3.3
Units
V
μA
V
V
μA
dBm
°C
PUP1
PUP2
GND
V
DD
V
DD
LE
PE
T
I
DD
Power Supply
Current
Digital Input High
0.7xV
DD
Digital Input Low
Digital Input Leakage
Input Power
Temperature range
-40
100
Table 2. Pin Descriptions
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Pin
Name
C16
RF1
Data
Clock
LE
V
DD
PUP1
PUP2
V
DD
GND
GND
Description
0.3xV
DD
1
RF port (Note 1).
Serial interface clock input.
Latch Enable input (Note 2).
Power supply pin.
Power-up selection bit.
Power-up selection bit.
Power supply pin.
Ground connection.
Ground connection.
43
Attenuation control bit, 16dB (Note 4).
Serial interface data input (Note 4).
+24
85
O
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Exposed Solder Pad Connection
The exposed solder pad on the bottom of the
package must be grounded for proper device
operation.
BS
C
V
ss
/GND
P/S
C8
C4
C2
Negative supply voltage or GND
connection (Note 3)
Parallel/Serial mode select.
RF port (Note 1).
RF2
Attenuation control bit, 8 dB.
Attenuation control bit, 4 dB.
Attenuation control bit, 2 dB.
GND
C1
N/C
Ground connection.
Attenuation control bit, 1 dB.
No connect
Ground for proper operation
GND
O
19
20
Paddle
EP
LA
©2003-2006 Peregrine Semiconductor Corp. All rights reserved.
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Notes: 1: Both RF ports must be held at 0 V
DC
or DC blocked with an
external series capacitor.
2: Latch Enable (LE) has an internal 100 kΩ resistor to V
DD.
3: Connect pin 12 to GND to enable internal negative voltage
generator. Connect pin 12 to V
SS
(-V
DD
) to bypass and
disable internal negative voltage generator.
4. Place a 10 kΩ resistor in series, as close to pin as possible
to avoid frequency resonance. See “Resistor on Pin 1 & 3”
paragraph
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Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS™ device, observe
the same precautions that you would use with other
ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the rate specified in Table 3.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
Switching Frequency
The PE4308 has a maximum 25 kHz switching rate.
Resistor on Pin 1 & 3
A 10 kΩ resistor on the inputs to Pin 1 & 3 (see
Figure 5) will eliminate package resonance between
the RF input pin and the two digital inputs. Specified
attenuation error versus frequency performance is
dependent upon this condition.
Document No. 70-0162-04
│
UltraCMOS™ RFIC Solutions
PE4308
Product Specification
Evaluation Kit
The Digital Attenuator Evaluation Kit was designed to
ease customer evaluation of the PE4308 DSA.
J9 is used in conjunction with the supplied DC cable to
supply V
DD
, GND, and –V
DD
. If use of the internal
negative voltage generator is desired, then connect
–V
DD
(black banana plug) to ground. If an external –V
DD
is desired, then apply -3 V.
J1 should be connected to the LPT1 port of a PC with
the supplied control cable. The evaluation software is
written to operate the DSA in serial mode, so switch 7
(P/S) on the DIP switch SW1 should be ON with all
other switches off. Using the software, enable or
disable each attenuation setting to the desired
combined attenuation. The software automatically
programs the DSA each time an attenuation state is
enabled or disabled. Note: Jumper J6 supplies power
to the evaluation board support circuits.
To evaluate the power up options, first disconnect the
control cable from the evaluation board. The control
cable must be removed to prevent the PC port from
biasing the control pins.
During power up with P/S=1 high and LE=1, the default
power-up signal attenuation is set to the value present
on the five control bits on the five parallel data inputs
(C1 to C16). This allows any one of the 32 attenuation
settings to be specified as the power-up state.
Figure 4. Evaluation Board Layout
Peregrine Specification 101/0112
During power up with P/S=0 high and LE=0, the control
bits are automatically set to one of four possible values
presented through the PUP interface. These four
values are selected by the two power-up control bits,
PUP1 and PUP2, as shown in the Table 6.
Pin 20 is open and can be connected to any bias.
BS
C
E
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Note: Resistors on pins 1 and 3 are
required and should be placed as close
to the part as possible to avoid package
resonance and meet error specifications
over frequency.
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PE
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Figure 5. Evaluation Board Schematic
Peregrine Specification 102/0142
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PE4308
Product Specification
Typical Performance Data (25°C, V
DD
= 3.0 V unless otherwise noted)
Figure 6. Insertion Loss (Zo=75 ohms)
Figure 7. Attenuation at Major steps
0
35
31dB
30
-1
25
-2
20
-3
15
10
LE
PE
T
8dB
4dB
5
0
2000
0
500
0
-10
-4
-5
0
500
1000
RF Frequency (MHz)
E
14
16dB
2dB
1dB
Insertion Loss (dB)
Attenuation (dB)
Figure 8. Input Return Loss at Major
Attenuation Steps (Zo=75 ohms)
0
O
8dB
Figure 9. Output Return Loss at Major
Attenuation Steps (Zo=75 ohms)
-10
BS
C
Output Return Loss (dB)
Input Return Loss (dB)
-20
E
O
-30
16dB
31dB
-40
EP
LA
-50
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-20
-30
-40
-50
1500
2000
0
500
1000
RF Frequency (MHz)
1500
2000
0
500
1000
RF Frequency (MHz)
©2003-2006 Peregrine Semiconductor Corp. All rights reserved.
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Document No. 70-0162-04
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UltraCMOS™ RFIC Solutions
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43
1500
1000
1500
2000
RF Frequency (MHz)
PE4308
Product Specification
Typical Performance Data (25°C, V
DD
= 3.0 V unless otherwise noted)
Figure 10. Attenuation Error Vs. Frequency
Figure 11. Attenuation Error Vs. Attenuation
Setting
0.4
10MHz, -40C
0.5
2dB
0
0.2
10MHz, 25C
Attenuation Error (dB)
Attenuation Error (dB)
-0.5
16dB
-0.2
-1
31dB
-1.5
-2
0
500
1000
RF Frequency (MHz)
1500
LE
PE
T
-0.4
-0.6
-0.8
Figure 12. Attenuation Error Vs. Attenuation
Setting
0.4
BS
C
0.2
Attenuation Error (dB)
Attenuation Error (dB)
0
500MHz, 25C
-0.2
E
500MHz, 85C
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500MHz, -40C
20
25
30
35
Figure 13. Attenuation Error Vs. Attenuation
Setting
0.4
0.2
0
-0.2
43
10
15
20
2000
0
E
14
5
10
15
20
25
Attenuation Setting (dB)
5
25
Attenuation Setting (dB)
8dB
0
10MHz, 85C
30
35
O
1GHz, -40C
-0.4
1GHz, 25C
-0.6
1GHz, 85C
-0.4
-0.6
EP
LA
-0.8
-0.8
0
30
35
0
5
10
15
Attenuation Setting (dB)
Note: Positive attenuation error indicates higher attenuation than target value
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©2003-2006 Peregrine Semiconductor Corp. All rights reserved.
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