QP82530-6 datasheet, PDF - EEWORLD Datasheet

QP82530-6: DescriptionMulti Protocol Controller, 2 Channel(s), 0.1875MBps, NMOS, PDIP40, DIP-40; CategoryThe embedded processor and controller Microcontrollers and processors; File Size36KB，1 Pages; ManufacturerIntel; Websitehttp://www.intel.com/

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QP82530-6 Overview

Multi Protocol Controller, 2 Channel(s), 0.1875MBps, NMOS, PDIP40, DIP-40

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Intel
Parts packaging code	DIP
package instruction	DIP, DIP40,.6
Contacts	40
Reach Compliance Code	compliant
boundary scan	NO
Bus compatibility	MCS 51; MCS 96; IAPX 86; IAPX 88; IAPX 186; IAPX 188
maximum clock frequency	6 MHz
letter of agreement	ASYNC, BIT; SYNC, BYTE; SYNC, SDLC; X.25; BISYNC; EXT SYNC
Data encoding/decoding methods	NRZ; NRZI-SPACE; BIPH-MARK(FM1); BIPH-SPACE(FM0); BIPH-LEVEL(MANCHESTER)
Maximum data transfer rate	0.1875 MBps
External data bus width	8
JESD-30 code	R-PDIP-T40
JESD-609 code	e0
length	52.26 mm
low power mode	NO
Number of DMA channels
Number of I/O lines	8
Number of serial I/Os	2
Number of terminals	40
On-chip data RAM width
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Encapsulate equivalent code	DIP40,.6
Package shape	RECTANGULAR
Package form	IN-LINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Certification status	Not Qualified
RAM (number of words)	0
Maximum seat height	5.08 mm
Nominal supply voltage	5 V
surface mount	NO
technology	NMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	15.24 mm
uPs/uCs/peripheral integrated circuit type	SERIAL IO/COMMUNICATION CONTROLLER, MULTI PROTOCOL

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