• Supports numerous SerDes Transmit Voltage Margin
settings
– Unused SerDes are disabled
Testability and Debug Features
– Built in Pseudo-Random Bit Stream (PRBS) generator
– Numerous SerDes test modes
– Ability to read and write any internal register via the SMBus
– Ability to bypass link training and force any link into any mode
– Provides statistics and performance counters
General Purpose Input/Output Pins
– Each pin may be individually configured as an input or output
– Each pin may be individually configured as an interrupt input
– Some pins have selectable alternate functions
Packaged in a 19mm x 19mm, 324-ball BGA with 1mm ball
spacing
Processor
Processor
North
Bridge
Memory
Memory
Memory
Memory
x1
PES4T4G2
x1
PCI Express
Slot
x1
I/O
4xGbE
x1
I/O
4xGbE
I/O
SATA
I/O
SATA
Figure 2 I/O Expansion Application
SMBus Interface
The PES4T4G2 contains two SMBus interfaces. The slave interface
provides full access to the configuration registers in the PES4T4G2,
allowing every configuration register in the device to be read or written
by an external agent. The master interface allows the default configura-
tion register values of the PES4T4G2 to be overridden following a reset
with values programmed in an external serial EEPROM. The master
interface is also used by an external Hot-Plug I/O expander.
Two pins make up each of the two SMBus interfaces. These pins
consist of an SMBus clock pin and an SMBus data pin. The Master
SMBus address is hardwired to 0x50, and the slave SMBus address is
hardwired to 0x77.
As shown in Figure 3, the master and slave SMBuses may be used
in a unified or split configuration. In the unified configuration, shown in
Figure 3(a), the master and slave SMBuses are tied together and the
PES4T4G2 acts both as a SMBus master as well as a SMBus slave on
this bus. This requires that the SMBus master or processor that has
access to PES4T4G2 registers supports SMBus arbitration. In some
systems, this SMBus master interface may be implemented using
general purpose I/O pins on a processor or micro controller, and may
not support SMBus arbitration. To support these systems, the
PES4T4G2 may be configured to operate in a split configuration as
shown in Figure 3(b).
In the split configuration, the master and slave SMBuses operate as
two independent buses and thus multi-master arbitration is never
required. The PES4T4G2 supports reading and writing of the serial
EEPROM on the master SMBus via the slave SMBus, allowing in
system programming of the serial EEPROM.
Product Description
Utilizing standard PCI Express interconnect the PES4T4G2 provides
the most efficient high-performance I/O connectivity device for applica-
tions requiring high throughput, low latency and simple board layout. It
provides PCI Express connectivity across 4 lanes and 4 ports. Each
lane provides 5 Gbps of bandwidth in both directions and is fully
compliant with PCI Express Base specification 2.0.
The PES4T4G2 is based on a flexible and efficient layered architec-
ture. The PCI Express layer consists of SerDes, Physical, Data Link and
Transaction layers in compliance with PCI Express Base specification
Revision 2.0. The PES4T4G2 can operate either as a store and forward
or cut-through switch and is designed to switch memory and I/O transac-
tions. It supports eight Traffic Classes (TCs) and one Virtual Channel
(VC) with sophisticated resource management to enable efficient
switching and I/O connectivity for servers, storage, and embedded
processors with limited connectivity.
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May 23, 2013
IDT 89HPES4T4G2 Data Sheet
PES4T4G2
Processor
SMBus
Master
Serial
EEPROM
...
Other
SMBus
Devices
PES4T4G2
Processor
SMBus
Master
...
Other
SMBus
Devices
SSMBCLK
SSMBDAT
MSMBCLK
MSMBDAT
SSMBCLK
SSMBDAT
MSMBCLK
MSMBDAT
Serial
EEPROM
(a) Unified Configuration and Management Bus
(b) Split Configuration and Management Buses
Figure 3 SMBus Interface Configuration Examples
Hot-Plug Interface
The PES4T4G2 supports PCI Express Hot-Plug on each downstream port. To reduce the number of pins required on the device, the PES4T4G2
utilizes an external I/O expander, such as that used on PC motherboards, connected to the SMBus master interface. Following reset and configura-
tion, whenever the state of a Hot-Plug output needs to be modified, the PES4T4G2 generates an SMBus transaction to the I/O expander with the new
value of all of the outputs. Whenever a Hot-Plug input changes, the I/O expander generates an interrupt which is received on the IOEXPINTN input pin
(alternate function of GPIO) of the PES4T4G2. In response to an I/O expander interrupt, the PES4T4G2 generates an SMBus transaction to read the
state of all of the Hot-Plug inputs from the I/O expander.
General Purpose Input/Output
The PES4T4G2 provides 7 General Purpose Input/Output (GPIO) pins that may be used by the system designer as bit I/O ports. Each GPIO pin
may be configured independently as an input or output through software control. Most GPIO pins are shared with other on-chip functions. These alter-
nate functions may be enabled via software, SMBus slave interface, or serial configuration EEPROM.
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May 23, 2013
IDT 89HPES4T4G2 Data Sheet
Pin Description
The following tables list the functions of the pins provided on the PES4T4G2. Some of the functions listed may be multiplexed onto the same pin.
The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low)
level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level.
Signal
PE0RP[0]
PE0RN[0]
PE0TP[0]
PE0TN[0]
PE1RP[0]
PE1RN[0]
PE1TP[0]
PE1TN[0]
PE2RP[0]
PE2RN[0]
PE2TP[0]
PE2TN[0]
PE3RP[0]
PE3RN[0]
PE3TP[0]
PE3TN[0]
PEREFCLKP
PEREFCLKN
Type
I
O
I
O
I
O
I
O
I
Name/Description
PCI Express Port 0 Serial Data Receive.
Differential PCI Express receive
pair for port 0. Port 0 is the upstream port.
PCI Express Port 0 Serial Data Transmit.
Differential PCI Express trans-
mit pair for port 0. Port 0 is the upstream port.
PCI Express Port 1 Serial Data Receive.
Differential PCI Express receive
pair for port 1.
PCI Express Port 1 Serial Data Transmit.
Differential PCI Express trans-
mit pair for port 1.
PCI Express Port 2 Serial Data Receive.
Differential PCI Express receive
pair for port 2.
PCI Express Port 2 Serial Data Transmit.
Differential PCI Express trans-
mit pair for port 2.
PCI Express Port 3 Serial Data Receive.
Differential PCI Express receive
pair for port 3.
PCI Express Port 3 Serial Data Transmit.
Differential PCI Express trans-
mit pair for port 3.
PCI Express Reference Clock.
Differential reference clock pair input. This
clock is used as the reference clock by on-chip PLLs to generate the clocks
required for the system logic and on-chip SerDes. The frequency of the dif-
ferential reference clock is set at 100MHz.
Table 1 PCI Express Interface Pins
Signal
MSMBCLK
MSMBDAT
SSMBCLK
SSMBDAT
Type
I/O
I/O
I/O
I/O
Name/Description
Master SMBus Clock.
This bidirectional signal is used to synchronize
transfers on the master SMBus which operates at 400 KHz.
Master SMBus Data.
This bidirectional signal is used for data on the mas-
ter SMBus which operates at 400 KHz.
Slave SMBus Clock.
This bidirectional signal is used to synchronize trans-
fers on the slave SMBus.
Slave SMBus Data.
This bidirectional signal is used for data on the slave
SMBus.
Table 2 SMBus Interface Pins
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May 23, 2013
IDT 89HPES4T4G2 Data Sheet
Signal
GPIO[0]
Type
I/O
Name/Description
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P2RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 2.
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
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