FemtoClock
®
NG Crystal-to-LVCMOS/
LVTTL Clock Synthesizer
General Description
The ICS840N251I-45 is a LVCMOS/LVTTL clock synthesizer
designed for Ethernet applications. The device generates a
selectable 156.25MHz or 125MHz clock signal with excellent phase
jitter performance. The device uses IDT’s fourth generation
FemtoClock
®
NG technology for an optimum of high clock frequency,
low phase noise performance and low power consumption.The
device supports 2.5V or 3.3V voltage supply and is packaged in a
small, lead-free (RoHS 6) 8-lead TSSOP package. The extended
temperature range supports wireless infrastructure,
telecommunication and networking end equipment requirements.
Input
FREQ_SEL
0 (default)
1
Output Frequency
f
XTAL
= 25MHz
156.25MHz
125MHz
f
XTAL
= 20MHz
125MHz
100MHz
ICS840N251I-45
DATA SHEET
Features
•
•
•
•
•
•
•
•
•
•
Fourth generation FemtoClock
®
NG technology
156.25MHz output clock synthesized from a 25MHz fundamental
mode crystal
One2.5V or 3.3V LVCMOS/LVTTL clock output
Crystal interface designed for 25MHz,
12pF parallel resonant crystal
RMS phase jitter @ 125MHz, using a 25MHz crystal
(1.875MHz - 20MHz): 0.140ps (maximum)
RMS phase jitter @ 156.25MHz, using a 25MHz crystal
(12kHz - 20MHz): 0.416ps (maximum)
LVCMOS interface levels for the control inputs
Full 2.5V or 3.3V supply voltage
Available in lead-free (RoHS 6) package
-40°C to 85°C ambient operating temperature
NOTE: FREQ_SEL is an asynchronous control.
Input
OE
0
1 (default)
Output Enable
Output Q is disabled in high-impedance state
Output Q is enabled.
NOTE: OE is an asynchronous control.
Block Diagram
XTAL_IN
OSC
XTAL_OUT
PFD
&
LPF
FemtoClock
®
NG
VCO
490-637.5MHz
÷4,
÷5
Q
Pin Assignment
VDDA
OE
XTAL_OUT
XTAL_IN
1
2
3
8
7
6
5
VDD
Q
GND
FREQ_SEL
4
÷25
FREQ_SEL
OE
Pulldown
Pullup
ICS840N251I-45
8-lead TSSOP
4.40mm x 3.0mm x 0.925mm
package body
G Package
Top View
ICS840N251BGI-45 REVISION A MAY 16, 2012
1
©2012 Integrated Device Technology, Inc.
ICS840N251I-45 Data Sheet
FEMTOCLOCK
®
NG CRYSTAL-TO-LVCMOS/LVTTL CLOCK SYNTHESIZER
Table 1. Pin Descriptions
Number
1
2
3,
4
5
6
7
8
Name
V
DDA
OE
XTAL_OUT,
XTAL_IN
FREQ_SEL
GND
Q
V
DD
Power
Input
Input
Input
Power
Output
Power
Pulldown
Pullup
Type
Description
Analog power supply.
Output enable pin. LVCMOS interface levels.
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.
Frequency select pin. LVCMOS/LVTTL interface levels.
Power supply ground.
Single-ended clock output. LVCMOS/LVTTL interface levels.
Core supply pin.
NOTE:
Pulldown and Pullup
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
C
PD
R
PULLUP
R
PULLDOWN
R
OUT
Parameter
Input Capacitance
Power Dissipation
Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Output Impedance
V
DD
= 3.3V
V
DD
= 2.5V
V
DD
= 3.465V
V
DD
= 2.625V
Test Conditions
Minimum
Typical
3.5
11
9
51
51
15
19
Maximum
Units
pF
pF
pF
k
k
ICS840N251BGI-45 REVISION A MAY 16, 2012
2
©2012 Integrated Device Technology, Inc.
ICS840N251I-45 Data Sheet
FEMTOCLOCK
®
NG CRYSTAL-TO-LVCMOS/LVTTL CLOCK SYNTHESIZER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
XTAL_IN
Other Inputs
Outputs, V
O
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
3.63V
0V to 2V
-0.5V to V
DD
+ 0.5V
-0.5V to V
DD
+ 0.5V
117°C/W (0 mps)
-65C to 150C
DC Electrical Characteristics
Table 3A. Power Supply DC Characteristics, V
DD
= 3.3V±5% or 2.5V±5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
DD
V
DDA
V
DDA
I
DDA
I
DD
Parameter
Core Supply Voltage
Analog Supply Voltage
Analog Supply Voltage
Analog Supply Current
Power Supply Current
Test Conditions
Minimum
2.375
V
DD
– 0.17
V
DD
– 0.17
Typical
3.3
3.3
2.5
Maximum
3.465
V
DD
V
DD
17
65
Units
V
V
V
mA
mA
Table 3B. LVCMOS/LVTTL DC Characteristics, V
DD
= 3.3V±5% or 2.5V±5%, T
A
= -40°C to 85°C
Symbol
V
IH
Parameter
Input High Voltage
Test Conditions
V
DD
= 3.3V
V
DD
= 2.5V
V
DD
= 3.3V
V
DD
= 3.3V, OE
V
IL
Input Low Voltage
V
DD
= 3.3V, FREQ_SEL
V
DD
= 2.5V
V
DD
= 2.5V, OE
V
DD
= 2.5V, FREQ_SEL
I
IH
Input High Current
FREQ_SEL
OE
FREQ_SEL
I
IL
Input Low Current
OE
V
OH
V
OL
Output High Voltage;
NOTE 1
Output Low Voltage;
NOTE 1
Q
Q
V
DD
= V
IN
= 3.465V or 2.625V
V
DD
= V
IN
= 3.465V or 2.625V
V
DD
= 3.465V or 2.625V,
V
IN
= 0V
V
DD
= 3.465V or 2.625V,
V
IN
= 0V
V
DD
= 3.465V
V
DD
= 2.625V
V
DD
= 3.465V or 2.625V
-5
-150
2.6
1.8
0.5
Minimum
2
1.7
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
Typical
Maximum
V
DD
+ 0.3
V
DD
+ 0.3
0.8
0.8
0.5
0.7
0.7
0.5
150
5
Units
V
V
V
V
V
V
V
V
µA
µA
µA
µA
V
V
V
NOTE 1: Output terminated with 50
to V
DD
/ 2. See Parameter Measurement Information Section,
LVCMOS Output Load Test Circuit Diagrams.
ICS840N251BGI-45 REVISION A MAY 16, 2012
3
©2012 Integrated Device Technology, Inc.
ICS840N251I-45 Data Sheet
FEMTOCLOCK
®
NG CRYSTAL-TO-LVCMOS/LVTTL CLOCK SYNTHESIZER
Table 4. Crystal Characteristics
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
19.6
Test Conditions
Minimum
Typical
Fundamental
25
25.5
80
7
MHz
Maximum
Units
pF
AC Characteristics
Table 5. AC Characteristics, V
DD
= 3.3V±5% or 2.5V±5%, T
A
= -40°C to 85°C
Symbol
f
OUT
Parameter
Output Frequency
Test Conditions
FREQ_SEL = 0
FREQ_SEL = 1
f
OUT
= 156.25MHz, 25MHz crystal,
Integration Range: 1.875MHz – 20MHz
RMS Phase Jitter (Random);
NOTE 1
f
OUT
= 156.25MHz, 25MHz crystal,
Integration Range: 12kHz – 20MHz
f
OUT
= 125MHz, 25MHz crystal,
Integration Range: 1.875MHz – 20MHz
f
OUT
= 125MHz, 25MHz crystal,
Integration Range: 12kHz – 20MHz
f
OUT
= 156.25MHz, Offset: 10Hz
f
OUT
= 156.25MHz, Offset: 100Hz
N
Single-Side Band
Noise Power
f
OUT
= 156.25MHz, Offset: 1kHz
f
OUT
= 156.25MHz, Offset: 10kHz
f
OUT
= 156.25MHz, Offset: 100kHz
f
OUT
= 156.25MHz, Offset: 1MHz
f
OUT
= 156.25MHz, Offset: 10MHz
t
R
/ t
F
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
200
48
Minimum
122.5
98.0
Typical
156.25
125
0.107
0.358
0.109
0.357
-51.9
-76.9
-108.3
-124.6
-129.7
-139.6
-156.1
600
52
Maximum
159.38
127.5
0.143
0.416
0.140
0.378
Units
MHz
MHz
ps
ps
ps
ps
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
ps
%
tjit(Ø)
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal
equilibrium has been reached under these conditions.
NOTE: Characterized with a 20MHz and 25MHz crystal.
NOTE 1: Refer to the phase noise plots.
ICS840N251BGI-45 REVISION A MAY 16, 2012
4
©2012 Integrated Device Technology, Inc.
ICS840N251I-45 Data Sheet
FEMTOCLOCK
®
NG CRYSTAL-TO-LVCMOS/LVTTL CLOCK SYNTHESIZER
Typical Phase Noise at 125MHz (12kHz - 20MHz)
Noise Power dBc
Hz
Offset Frequency (Hz)
Typical Phase Noise at 125MHz (1.875MHz - 20MHz)
Noise Power dBc
Hz
Offset Frequency (Hz)
ICS840N251BGI-45 REVISION A MAY 16, 2012
5
©2012 Integrated Device Technology, Inc.
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