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MT47H32M16FT-5

Description
DDR DRAM, 32MX16, 0.6ns, CMOS, PBGA92, 11 X 19 MM, FBGA-92
Categorystorage    storage   
File Size4MB,94 Pages
ManufacturerMicron Technology
Websitehttp://www.mdtic.com.tw/
Download Datasheet Parametric Compare View All

MT47H32M16FT-5 Overview

DDR DRAM, 32MX16, 0.6ns, CMOS, PBGA92, 11 X 19 MM, FBGA-92

MT47H32M16FT-5 Parametric

Parameter NameAttribute value
MakerMicron Technology
Parts packaging codeBGA
package instruction11 X 19 MM, FBGA-92
Contacts92
Reach Compliance Codeunknown
ECCN codeEAR99
access modeFOUR BANK PAGE BURST
Maximum access time0.6 ns
Other featuresAUTO/SELF REFRESH
JESD-30 codeR-PBGA-B92
JESD-609 codee1
length19 mm
memory density536870912 bit
Memory IC TypeDDR DRAM
memory width16
Number of functions1
Number of ports1
Number of terminals92
word count33554432 words
character code32000000
Operating modeSYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature
organize32MX16
Package body materialPLASTIC/EPOXY
encapsulated codeTFBGA
Package shapeRECTANGULAR
Package formGRID ARRAY, THIN PROFILE, FINE PITCH
Certification statusNot Qualified
Maximum seat height1.2 mm
self refreshYES
Maximum supply voltage (Vsup)1.9 V
Minimum supply voltage (Vsup)1.7 V
Nominal supply voltage (Vsup)1.8 V
surface mountYES
technologyCMOS
Temperature levelOTHER
Terminal surfaceTIN SILVER COPPER
Terminal formBALL
Terminal pitch0.8 mm
Terminal locationBOTTOM
width11 mm
PRELIMINARY
512Mb: x4, x8, x16
DDR2 SDRAM
DDR2 SDRAM
Features
V
DD
= +1.8V ±0.1V, V
DD
Q = +1.8V ±0.1V
JEDEC standard 1.8V I/O (SSTL_18-compatible)
Differential data strobe (DQS, DQS#) option
Four-bit prefetch architecture
Duplicate output strobe (RDQS) option for x8
configuration
DLL to align DQ and DQS transitions with CK
Four internal banks for concurrent operation
Programmable CAS Latency (CL): 3 and 4
Posted CAS additive latency (AL): 0, 1, 2, 3, and 4
WRITE latency = READ latency - 1
t
CK
Programmable burst lengths: 4 or 8
Supports READ burst interrupt by another READ
Supports WRITE burst interrupt by another WRITE
Adjustable data-output drive strength
64ms, 8,192-cycle refresh
On-die termination (ODT)
Supports the JEDEC DDR2 functionality
requirements
Designation
MT47H128M4 – 32 MEG X 4 X 4 BANKS
MT47H64M8 – 16 MEG X 8 X 4 BANKS
MT47H32M16 – 8 MEG X 16 X 4 BANKS
For the latest data sheet, please refer to the Micron Web
site:
http://www.micron.com/datasheets
ARCHITECTURE 128 MEG X 4
Configuration
Refresh Count
32 Meg x 4 x 4
banks
8K
16K (A0-A13)
4 (BA0, BA1)
2K (A0-A9, A11)
64 MEG X 8 32 MEG X 16
16 Meg x 8 x 4 8 Meg x 16 x 4
banks
banks
8K
16K (A0-A13)
4 (BA0, BA1)
1K (A0-A9)
8K
8K (A0-A12)
4 (BA0, BA1)
1K (A0-A9)
Options
• Configuration
128 Meg x 4 (32 Meg x 4 x 4 banks)
64 Meg x 8 (16 Meg x 8 x 4 banks)
32 Meg x 16 (8 Meg x 16 x 4 banks)
• FBGA Package
92-ball (11mm x 19mm) FBGA
• Timing – Cycle Time
5.0ns @ CL = 4 (DDR2-400)
5.0ns @ CL = 3 (DDR2-400)
3.75ns @ CL = 4 (DDR2-533)
128M4
64M8
32M16
FT
-5
-5E
-37E
Row Addressing
Bank
Addressing
Column
Addressing
Table 1:
SPEED
GRADE
-5
-5E
-37E
Key Timing Parameters
DATA RATE
(MHz)
CL = 3
400
400
CL = 4
400
400
533
t
RCD
(ns)
20
15
15
RP
(ns)
20
15
15
t
RC
(ns)
65
60
60
t
09005aef80b88542
512MbDDR2_1.fm - Rev. A 11/03 EN
1
©2003 Micron Technology, Inc. All rights reserved.
PRODUCTS
AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY
MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS.

MT47H32M16FT-5 Related Products

MT47H32M16FT-5 MT47H128M4FT-5 MT47H32M16FT-5E
Description DDR DRAM, 32MX16, 0.6ns, CMOS, PBGA92, 11 X 19 MM, FBGA-92 DDR DRAM, 128MX4, 0.6ns, CMOS, PBGA92, 11 X 19 MM, FBGA-92 DDR DRAM, 32MX16, 0.6ns, CMOS, PBGA92, 11 X 19 MM, FBGA-92
Maker Micron Technology Micron Technology Micron Technology
Parts packaging code BGA BGA BGA
package instruction 11 X 19 MM, FBGA-92 TFBGA, 11 X 19 MM, FBGA-92
Contacts 92 92 92
Reach Compliance Code unknown compliant unknown
ECCN code EAR99 EAR99 EAR99
access mode FOUR BANK PAGE BURST FOUR BANK PAGE BURST FOUR BANK PAGE BURST
Maximum access time 0.6 ns 0.6 ns 0.6 ns
Other features AUTO/SELF REFRESH AUTO/SELF REFRESH AUTO/SELF REFRESH
JESD-30 code R-PBGA-B92 R-PBGA-B92 R-PBGA-B92
JESD-609 code e1 e1 e1
length 19 mm 19 mm 19 mm
memory density 536870912 bit 536870912 bit 536870912 bit
Memory IC Type DDR DRAM DDR DRAM DDR DRAM
memory width 16 4 16
Number of functions 1 1 1
Number of ports 1 1 1
Number of terminals 92 92 92
word count 33554432 words 134217728 words 33554432 words
character code 32000000 128000000 32000000
Operating mode SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS
Maximum operating temperature 85 °C 85 °C 85 °C
organize 32MX16 128MX4 32MX16
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code TFBGA TFBGA TFBGA
Package shape RECTANGULAR RECTANGULAR RECTANGULAR
Package form GRID ARRAY, THIN PROFILE, FINE PITCH GRID ARRAY, THIN PROFILE, FINE PITCH GRID ARRAY, THIN PROFILE, FINE PITCH
Certification status Not Qualified Not Qualified Not Qualified
Maximum seat height 1.2 mm 1.2 mm 1.2 mm
self refresh YES YES YES
Maximum supply voltage (Vsup) 1.9 V 1.9 V 1.9 V
Minimum supply voltage (Vsup) 1.7 V 1.7 V 1.7 V
Nominal supply voltage (Vsup) 1.8 V 1.8 V 1.8 V
surface mount YES YES YES
technology CMOS CMOS CMOS
Temperature level OTHER OTHER OTHER
Terminal surface TIN SILVER COPPER TIN SILVER COPPER TIN SILVER COPPER
Terminal form BALL BALL BALL
Terminal pitch 0.8 mm 0.8 mm 0.8 mm
Terminal location BOTTOM BOTTOM BOTTOM
width 11 mm 11 mm 11 mm
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