QuickRAM Family Data Sheet
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QuickRAM ESP Combining Performance, Density and
Embedded RAM
Device Highlights
High Performance & High Density
• Up to 90,000 usable PLD gates with up to
316 I/Os
• 300 MHz 16-bit counters, 400 MHz datapaths,
160+ MHz FIFOs
• 0.35 µm four-layer metal non-volatile CMOS
process
Up to 316 I/O Pins
• Up to 308 bi-directional input/output pins,
PCI-compliant for 5.0 V and 3.3 V buses for
-1/-2/-3/-4 speed grades
• Eight high-drive input/distributed network pins
Eight Low-Skew Distributed
Networks
• Two array clock/control networks are available to
the logic cell flip-flop; clock, set, and reset inputs
— each can be driven by an input-only pin
• Six global clock/control networks available to the
logic cell; F1, clock, set, and reset inputs and the
data input, I/O register clock, reset, and enable
inputs as well as the output enable control—each
can be driven by an input-only, I/O pin, any logic
cell output, or I/O cell feedback
High Speed Embedded SRAM
• Up to 22 dual-port RAM modules, organized in
user-configurable 1,152 bit blocks
• 5 ns access times, each port independently
accessible
• Fast and efficient for FIFO, RAM, and ROM
functions
High Performance Silicon
• Input + logic cell + output total delays under 6 ns
• Data path speeds over 400 MHz
• Counter speeds over 300 MHz
• FIFO speeds over 160+ MHz
Figure 1: QuickRAM Block Diagram
Easy to Use/Fast Development
Cycles
• 100% routable with 100% utilization and
complete pin-out stability
• Variable-grain logic cells provide high
performance and 100% utilization
• Comprehensive design tools include high quality
Verilog/VHDL synthesis
Advanced I/O Capabilities
• Interfaces with 3.3 V and 5.0 V devices
• PCI compliant with 3.3 V and 5.0 V busses for
-1/-2/-3/-4 speed grades
• Full JTAG boundary scan
• I/O cells with individually controlled registered
input path and output enables
© 2007 QuickLogic Corporation
www.quicklogic.com
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RAM
Blocks
1,584
Hi gh Speed
Logic Cells
Interface
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QuickRAM Family Data Sheet Rev. M
Table 1: QuickRAM Product Family Members
QL4009
Max Gates
Logic Array
Logic Cells
Max Flip-Flops
Max I/O
RAM Modules
RAM Bits
PLCC
TQFP
Packages
PQFP
PBGA
CQFP
44,964
16 x 16
160
242
74
8
9,216
68/84
100
-
-
-
QL4016
61,820
20 x 16
320
438
110
10
11,520
84
100/144
-
-
100
QL4036
97,128
28 x 24
672
876
196
14
16,128
-
144
208
256
-
QL4058
131,328
36 x 28
1,008
1,260
244
18
20,736
-
-
208/240
456
-
QL4090
176,608
44 x 36
1,584
1,900
308
22
25,334
-
-
208/240
456
208
Table 2: Max I/O per Device/Package Combination
Device
QL4009
QL4016
QL4036
QL4058
QL4090
68
PLCC
46
-
-
-
-
84
PLCC
60
60
-
-
-
100
TQFP
74
74
-
-
-
144
TQFP
-
110
110
-
-
208
PQFP
-
-
166
166
166
240
PQFP
-
-
-
194
194
256
PBGA
-
-
196
-
-
456
PBGA
-
-
-
244
308
100
CQFP
-
74
-
-
-
208
CQFP
-
-
-
-
166
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© 2007 QuickLogic Corporation
QuickRAM Family Data Sheet Rev. M
Architecture Overview
The QuickRAM
TM
family of Embedded Standard Products (ESP) offer FPGA logic in combination with Dual-
Port SRAM modules. The QuickRAM family of ESPs have up to 90,000 usable PLD gates. QuickRAM ESPs
are fabricated on a 0.35 µm four-layer metal process using QuickLogic's patented ViaLink
TM
technology to
provide a unique combination of high performance, high density, low cost, and extreme ease-of-use.
The QuickRAM family contains a range of 160 to 1,584 logic cells and 8 to 22 dual port RAM Modules
(see
Figure 1).
Each RAM Module has 1,152 RAM bits, for a total ranging from 9,216 to 25,344 bits (see
Table 1).
RAM Modules are dual port (one read port, one write port) and can be configured into one of four
modes: 64 (deep) x18 (wide), 128x9, 256x4, or 512x2 (see
Figure 2).
With a maximum of 308 I/Os, the
QuickRAM family of ESPs are available in many device/package combinations (see
Table 2).
Figure 2: QuickRAM Module
[8:0]
[17:0]
WA
WD
WE
WCLK
RE
RCLK
RA
RD
ASYNCRD
[8:0]
[17:0]
[1:0]
MODE
Designers can cascade multiple RAM Modules to increase the depth or width allowed in single modules by
connecting corresponding address lines together and dividing the words between modules (see
Figure 3).
This
approach allows up to 512-deep configurations as large as 16 bits wide in the smallest QuickRAM device and
44 bits wide in the largest device.
Figure 3: QuickRAM Module Bits
WDATA
RAM
Module
(1,152 bits)
RDATA
WADDR
RADDR
RAM
Module
(1,152 bits)
WDATA
RDATA
© 2007 QuickLogic Corporation
www.quicklogic.com
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QuickRAM Family Data Sheet Rev. M
Software support for the complete QuickRAM family is available through two basic packages. The turnkey
QuickWorks
TM
package provides the most complete ESP software solution from design entry to logic
synthesis, to place and route, to simulation. The QuickTools
TM
packages provides a solution for designers who
use Cadence, Exemplar, Mentor, Synopsys, Synplicity, Viewlogic, Aldec, or other third-party tools for design
entry, synthesis, or simulation.
The QuickLogic variable grain logic cell features up to 16 simultaneous inputs and 5 outputs within a cell that
can be fragmented into 5 independent cells. Each cell has a fan-in of 29 including register and control lines
(see
Figure 4).
Figure 4: QuickRAM Logic Cell
QS
A1
A2
A3
A4
A5
A6
QS
OP
B1
B2
C1
C2
MP
MS
D1
D2
E1
E2
NP
NS
F1
F2
F3
F4
F5
F6
QC
QR
AZ
OZ
QZ
NZ
FZ
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© 2007 QuickLogic Corporation
QuickRAM Family Data Sheet Rev. M
Electrical Specifications
AC Characteristics at V
CC
= 3.3 V, T
A
= 25° C (K = 1.00)
To calculate delays, multiply the appropriate K factor from
Table 12
by the numbers provided in
Table 3
through
Table 10.
Table 3: Logic Cell
Symbol
t
PD
t
SU
t
H
t
CLK
t
CWHI
t
CWLO
t
SET
t
RESET
t
SW
t
RW
Parameter
Combinatorial Delay
a
Setup
Time
a
Hold Time
Clock to Q Delay
Clock High Time
Clock Low Time
Set
Delay
Reset Delay
Set
Width
Reset Width
Propagation Delays (ns) Fanout
1
1.4
1.7
0.0
0.7
1.2
1.2
1.0
0.8
1.9
1.8
2
1.7
1.7
0.0
1.0
1.2
1.2
1.3
1.1
1.9
1.8
3
1.9
1.7
0.0
1.2
1.2
1.2
1.5
1.3
1.9
1.8
4
2.2
1.7
0.0
1.5
1.2
1.2
1.8
1.6
1.9
1.8
5
3.2
1.7
0.0
2.5
1.2
1.2
2.8
2.6
1.9
1.8
a. These limits are derived from a representative
selection
of the
slowest
paths through the QuickRAM logic cell including typical net
delays. Worst case delay values for
specific
paths
should
be determined from timing analysis of your particular design.
Table 4: RAM Cell
Synchronous
Write Timing
Symbol
t
SWA
t
HWA
t
SWD
t
HWD
t
SWE
t
HWE
t
WCRD
Parameter
WA
Setup
Time to WCLK
WA Hold Time to WCLK
WD
Setup
Time to WCLK
WD Hold Time to WCLK
WE
Setup
Time to WCLK
WE Hold Time to WCLK
WCLK to RD (WA=RA)
a
Propagation Delays (ns) Fanout
1
1.0
0.0
1.0
0.0
1.0
0.0
5.0
2
1.0
0.0
1.0
0.0
1.0
0.0
5.3
3
1.0
0.0
1.0
0.0
1.0
0.0
5.6
4
1.0
0.0
1.0
0.0
1.0
0.0
5.9
5
1.0
0.0
1.0
0.0
1.0
0.0
7.1
a.
Stated
timing for worst case Propagation Delay over process variation at V
CC
= 3.3 V and T
A
= 25
°
C. Multiply by the appropriate
Delay Factor, K, for
speed
grade, voltage and temperature
settings
as
specified
in the Operating Range.
© 2007 QuickLogic Corporation
www.quicklogic.com
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