CAT93C86
16 Kb Microwire Serial
EEPROM
Description
The CAT93C86 is a 16 Kb Serial EEPROM memory device which
is configured as either registers of 16 bits (ORG pin at V
CC
) or 8 bits
(ORG pin at GND). Each register can be written (or read) serially by
using the DI (or DO) pin. The CAT93C86 is manufactured using
ON Semiconductor’s advanced CMOS EEPROM floating gate
technology. The device is designed to endure 1,000,000 program/erase
cycles and has a data retention of 100 years. The device is available in
8−pin DIP and 8−pin SOIC packages.
Features
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SOIC−8
V, W SUFFIX
CASE 751BD
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High Speed Operation: 3 MHz / V
CC
= 5 V
Low Power CMOS Technology
1.8 V to 5.5 V Operation
Selectable x8 or x16 Memory Organization
Self−timed Write Cycle with Auto−clear
Hardware and Software Write Protection
Power−up Inadvertent Write Protection
Sequential Read
Program Enable (PE) Pin
1,000,000 Program/Erase Cycles
100 Year Data Retention
Industrial and Extended Temperature Ranges
8−lead PDIP and SOIC Packages
These Devices are Pb−Free, Halogen Free/BFR Free, and RoHS
Compliant
V
CC
PDIP−8
L SUFFIX
CASE 646AA
SOIC−8
X SUFFIX
CASE 751BE
PIN CONFIGURATION
CS
SK
DI
DO
1
V
CC
PE
ORG
GND
PE
V
CC
CS
SK
1
ORG
GND
DO
DI
PDIP (L), SOIC (V, X)
SOIC (W)*
PIN FUNCTION
Pin Name
CS
Function
Chip Select
Clock Input
Serial Data Input
Serial Data Output
Power Supply
Ground
Memory Organization
Program Enable
ORG
CS
SK
PE
CAT93C86
DI
DO
SK
DI
DO
V
CC
GND
ORG
PE
GND
Figure 1. Functional Symbol
Note:
When the ORG pin is connected to V
CC
, the x16 organization
is selected. When it is connected to ground, the x8 pin is selected. If
the ORG pin is left unconnected, then an internal pull−up device will
select the x16 organization.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
* Not Recommended for New Designs
©
Semiconductor Components Industries, LLC, 2013
October, 2013
−
Rev. 12
1
Publication Order Number:
CAT93C86/D
CAT93C86
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameters
Temperature Under Bias
Storage Temperature
Voltage on any Pin with Respect to Ground (Note 1)
V
CC
with Respect to Ground
Package Power Dissipation Capability (T
A
= 25°C)
Lead Soldering Temperature (10 seconds)
Output Short Circuit Current (Note 2)
Ratings
−55
to +125
−65
to +150
−2.0
to +V
CC
+2.0
−2.0
to +7.0
1.0
300
100
Units
°C
°C
V
V
W
°C
mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The minimum DC input voltage is
−0.5
V. During transitions, inputs may undershoot to
−2.0
V for periods of less than 20 ns. Maximum DC
voltage on output pins is V
CC
+0.5 V, which may overshoot to V
CC
+2.0 V for periods of less than 20 ns.
2. Output shorted for no more than one second. No more than one output shorted at a time.
Table 2. RELIABILITY CHARACTERISTICS
Symbol
N
END
(Note 3)
T
DR
(Note 3)
V
ZAP
(Note 3)
I
LTH
(Notes 3, 4)
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch−Up
Reference Test Method
MIL−STD−883, Test Method 1033
MIL−STD−883, Test Method 1008
MIL−STD−883, Test Method 3015
JEDEC Standard 17
Min
1,000,000
100
2000
100
Units
Cycles/Byte
Years
V
mA
3. These parameters are tested initially and after a design or process change that affects the parameter.
4. Latch−up protection is provided for stresses up to 100 mA on address and data pins from
−1
V to V
CC
+1 V.
Table 3. D.C. OPERATING CHARACTERISTICS
(V
CC
= +1.8 V to +5.5 V unless otherwise specified.)
Symbol
I
CC1
I
CC2
I
SB1
I
SB2
I
LI
I
LO
V
IL1
V
IH1
V
IL2
V
IH2
V
OL1
V
OH1
V
OL2
V
OH2
Parameter
Power Supply Current (Write)
Power Supply Current (Read)
Power Supply Current
(Standby) (x8 Mode)
Power Supply Current
(Standby) (x16 Mode)
Input Leakage Current
Output Leakage Current
(Including ORG pin)
Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
Test Conditions
f
SK
= 1 MHz; V
CC
= 5.0 V
f
SK
= 1 MHz; V
CC
= 5.0 V
CS = 0 V ORG = GND
CS = 0 V ORG = Float or V
CC
V
IN
= 0 V to V
CC
V
OUT
= 0 V to V
CC
, CS = 0 V
4.5 V
≤
V
CC
< 5.5 V
4.5 V
≤
V
CC
< 5.5 V
1.8 V
≤
V
CC
< 4.5 V
1.8 V
≤
V
CC
< 4.5 V
4.5 V
≤
V
CC
< 5.5 V; I
OL
= 2.1 mA
4.5 V
≤
V
CC
< 5.5 V; I
OH
=
−400
mA
1.8 V
≤
V
CC
< 4.5 V; I
OL
= 1 mA
1.8 V
≤
V
CC
< 4.5 V; I
OH
=
−100
mA
V
CC
−
0.2
2.4
0.2
−0.1
2
0
V
CC
x 0.7
0
Min
Typ
Max
3
500
10
10
1
1
0.8
V
CC
+ 1
V
CC
x 0.2
V
CC
+ 1
0.4
Units
mA
mA
mA
mA
mA
mA
V
V
V
V
V
V
V
V
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2
CAT93C86
Table 4. PIN CAPACITANCE
(Note 5)
Symbol
C
OUT
C
IN
Test
Output Capacitance (DO)
Input Capacitance (CS, SK, DI, ORG)
Conditions
V
OUT
= 0 V
V
IN
= 0 V
Min
Typ
Max
5
5
Units
pF
pF
Table 5. POWER−UP TIMING
(Notes 5, 6)
Symbol
t
PUR
t
PUW
Parameter
Power−up to Read Operation
Power−up to Write Operation
Max
1
1
Units
ms
ms
Table 6. A.C. TEST CONDITIONS
Input Rise and Fall Times
Input Pulse Voltages
Timing Reference Voltages
Input Pulse Voltages
Timing Reference Voltages
≤
50 ns
0.4 V to 2.4 V
0.8 V, 2.0 V
0.2 x V
CC
to 0.7 x V
CC
0.5 x V
CC
4.5 V
≤
V
CC
≤
5.5 V
4.5 V
≤
V
CC
≤
5.5 V
1.8 V
≤
V
CC
≤
4.5 V
1.8 V
≤
V
CC
≤
4.5 V
Table 7. A.C. CHARACTERISTICS
V
CC
=
1.8 V
−
5.5 V
Symbol
t
CSS
t
CSH
t
DIS
t
DIH
t
PD1
t
PD0
t
HZ
(Note 5)
t
EW
t
CSMIN
t
SKHI
t
SKLOW
t
SV
SK
MAX
5.
6.
7.
Parameter
CS Setup Time
CS Hold Time
DI Setup Time
DI Hold Time
Output Delay to 1
Output Delay to 0
Output Delay to High−Z
Program/Erase Pulse Width
Minimum CS Low Time
Minimum SK High Time
Minimum SK Low Time
Output Delay to Status Valid
Maximum Clock Frequency
DC
1
1
1
1
500
DC
C
L
= 100 pF (Note 7)
Test Conditions
Min
200
0
200
200
1
1
400
5
0.5
0.5
0.5
0.5
1000
DC
Max
V
CC
=
2.5 V
−
5.5 V
Min
100
0
100
100
0.5
0.5
200
5
0.15
0.15
0.15
0.1
3000
Max
V
CC
=
4.5 V
−
5.5 V
Min
50
0
50
50
0.15
0.15
100
5
Max
Units
ns
ns
ns
ns
ms
ms
ns
ms
ms
ms
ms
ms
kHz
These parameters are tested initially and after a design or process change that affects the parameter.
t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
The input levels and timing reference points are shown in the “A.C. Test Conditions” table.
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CAT93C86
Table 8. INSTRUCTION SET
Instruction
READ
ERASE
WRITE
EWEN
EWDS
ERAL
WRAL
Start
Bit
1
1
1
1
1
1
1
Address
Opcode
10
11
01
00
00
00
00
x8
A10−A0
A10−A0
A10−A0
11XXXXXXXXX
00XXXXXXXXX
10XXXXXXXXX
01XXXXXXXXX
x16
A9−A0
A9−A0
A9−A0
11XXXXXXXX
00XXXXXXXX
10XXXXXXXX
01XXXXXXXX
D7−D0
D15−D0
D7−D0
D15−D0
x8
Data
x16
Comments
Read Address AN– A0
Clear Address AN– A0
Write Address AN– A0
Write Enable
Write Disable
Clear All Addresses
Write All Addresses
Device Operation
The CAT93C86 is a 16,384−bit nonvolatile memory
intended for use with industry standard microprocessors.
The CAT93C86 can be organized as either registers of 16
bits or 8 bits. When organized as X16, seven 13−bit
instructions control the reading, writing and erase
operations of the device. When organized as X8, seven
14−bit instructions control the reading, writing and erase
operations of the device. The CAT93C86 operates on a
single power supply and will generate on chip, the high
voltage required during any write operation.
Instructions, addresses, and write data are clocked into the
DI pin on the rising edge of the clock (SK). The DO pin is
normally in a high impedance state except when reading data
from the device, or when checking the ready/busy status
after a write operation.
The ready/busy status can be determined after the start of
a write operation by selecting the device (CS high) and
polling the DO pin; DO low indicates that the write
operation is not completed, while DO high indicates that the
device is ready for the next instruction. If necessary, the DO
pin may be placed back into a high impedance state during
chip select by shifting a dummy “1” into the DI pin. The DO
pin will enter the high impedance state on the falling edge of
the clock (SK). Placing the DO pin into the high impedance
state is recommended in applications where the DI pin and
the DO pin are to be tied together to form a common DI/O
pin.
The format for all instructions sent to the device is a
logical “1” start bit, a 2−bit (or 4−bit) opcode, 10−bit address
(an additional bit when organized X8) and for write
operations a 16−bit data field (8−bit for X8 organizations).
Note:
The Write, Erase, Write all and Erase all instructions
require PE = 1. If PE is left floating, 93C86 is in Program
Enabled mode. For Write Enable and Write Disable
instruction PE = don’t care.
Read
Upon receiving a READ command and an address
(clocked into the DI pin), the DO pin of the CAT93C86 will
come out of the high impedance state and, after sending an
initial dummy zero bit, will begin shifting out the data
addressed (MSB first). The output data bits will toggle on
the rising edge of the SK clock and are stable after the
specified time delay (t
PD0
or t
PD1
).
After the initial data word has been shifted out and CS
remains asserted with the SK clock continuing to toggle, the
device will automatically increment to the next address and
shift out the next data word in a sequential READ mode. As
long as CS is continuously asserted and SK continues to
toggle, the device will keep incrementing to the next address
automatically until it reaches to the end of the address space,
then loops back to address 0. In the sequential READ mode,
only the initial data word is preceeded by a dummy zero bit.
All subsequent data words will follow without a dummy
zero bit.
Write
After receiving a WRITE command, address and the data,
the CS (Chip Select) pin must be deselected for a minimum
of t
CSMIN
. The falling edge of CS will start the self clocking
clear and data store cycle of the memory location specified
in the instruction. The clocking of the SK pin is not
necessary after the device has entered the self clocking
mode. The ready/busy status of the CAT93C86 can be
determined by selecting the device and polling the DO pin.
Since this device features Auto−Clear before write, it is
NOT necessary to erase a memory location before it is
written into.
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CAT93C86
t
SKHI
SK
t
DIS
DI
t
CSS
CS
t
DIS
DO
t
PD0
, t
PD1
DATA VALID
t
CSMIN
VALID
VALID
t
DIH
t
SKLOW
t
CSH
Figure 2. Synchronous Data Timing
SK
1
CS
A
N
DI
1
1
0
A
N−1
A
0
Don’t Care
1
1
1
1
1
1
1
1
1
1
1
1
1
1
DO
HIGH−Z
Dummy 0
D
15 . . .
D
0
or
D
7 . . .
D
0
Address +
1
D
15 . . .
D
0
or
D
7 . . .
D
0
Address +
2
D
15 . . .
D
0
or
D
7 . . .
D
0
Address + n
D
15 . . .
or
D
7 . . .
Figure 3. Read Instruction Timing
SK
t
CSMIN
CS
A
N
A
N−1
DI
1
0
1
HIGH−Z
t
SV
BUSY
READY
t
EW
t
HZ
HIGH−Z
A
0
D
N
D
0
STATUS
VERIFY
STANDBY
DO
Figure 4. Write Instruction Timing
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