256Mb C-die(x4/8) DDR SDRAM
DDR SDRAM Specification
Version 0.7
- 1 -
REV. 0.7 Jan. 31. 2002
256Mb C-die(x4/8) DDR SDRAM
Revision History
Version 0 (May, 2001)
- First version for internal review of 256Mb C-die.
Version 0.1 (July, 2001)
- Updated target current spec(TSOP package base)
- Add derating values for the specifications if the single-ended clock skew rate is less than 1.0V/ns in page 49.
Version 0.2 (September, 2001)
- Changed target spec to Prelieminary spec
Version 0.3 (September, 2001)
- Updated DC current spec
Version 0.4(October,2001)
-
Deleted WBGA product
- Modificated typo.
- Changed pin # 17 from NC to A13 in Package pinout.
- Revised "Write with autoprecharge" table in page 29.
- Added tIS and tPDEX parameters in "power down" timing of page 31.
- Revised "Absolute maximum rating" table in page 38.
. Changed "Voltage on VDDQ supply relative to VSS" value from -0.5~3.6V to -1~3.6V
. Changed "power dissipation" value from 1.0W to 1.5W.
- Revised AC parameter table
Version 0.5(November,2001)
From
DDR266A
Min.
tHZ(DQ)
tACmin
-400ps
tACmin
-400ps
Max.
tACmax
-400ps
tACmax
-400ps
DDR266B
Min.
tACmin
-400ps
tACmin
-400ps
Max.
tACmax
-400ps
tACmax
-400ps
DDR200
Min.
tACmin
-400ps
tACmin
-400ps
Max.
tACmax
-400ps
tACmax
-400ps
DDR266A
Min.
-0.75
Max.
+0.75
To
DDR266B
Min.
-0.75
Max.
+0.75
DDR200
Min.
-0.8
Max.
+0.8
tLZ(DQ)
tHZ(DQS)
tLZ(DQS)
tWPST
(tCK)
tPDEX
-0.75
-0.75
-0.75
+0.75
+0.75
+0.75
0.6
-0.75
-0.75
-0.75
0.4
7.5ns
+0.75
+0.75
+0.75
0.6
-0.8
-0.8
-1.1
0.4
10ns
+0.8
+0.8
-0.8
0.6
0.25
10ns
0.25
10ns
0.25
10ns
0.4
7.5ns
- Deleted "preliminary"
- Deleted tHZ/tLZ of DQS
Version 0.6(November,2001)
-
Updated DDR333 test specification
-
Deleted typical current in IDD spec. table
-
Included address and control input setup/hold time(tIS/tIH) at slow slew rate in DDR200/266 AC specification
-
Deleted Exit self refresh to write command(tXSW) in DDR200/266 AC specification
-
Changed unit of tMRD from tCK to ns at DDR333
-
Rename tXSA(exit self refresh to bank active command) to tXSNR(exit self refresh to non read command) at DDR200/266
-
Rename tXSR(exit self refresh to read command) to tXSRD at DDR200/266
-
Rename tWPREH(DQS in hold time) to tWPRE at DDR200/266
-
Rename tREF(Refresh interval time) to tREFI at DDR200/266
- Changed tWR value from 2tCK to 15ns.
- Added tDAL(tWR+tRP)
- Rename tCDLR to tWTR
- Updated current value
- 2 -
REV. 0.7 Jan. 31. 2002
256Mb C-die(x4/8) DDR SDRAM
Revision History
Version 0.7 (January, 2002)
- Added tRAP(Active to read with auto precharge command)
- 3 -
REV. 0.7 Jan. 31. 2002
256Mb C-die(x4/8) DDR SDRAM
Contents
Revision History
General Information
1. Key Features
1.1 Features
1.2 Operating Frequencies
2. Package Pinout & Dimension
2.1 Package Pintout
2.1.1 66pin TSOP II
2.2 Input/Output Function Description
2.3 Package Physical dimension
2.3.1 66 Pin TSOP(II)/MS-024FC Package Physical Dimension
3. Functional Description
3.1 Simplified State Diagram
3.2 Basic Functionality
3.2.1 Power-Up Sequence
3.2.2 Mode Register Definition
3.2.2.1 Mode Register Set(MRS)
3.2.2.2 Extended Mode Register Set(EMRS)
3.2.3 Precharge
3.2.4 No Operation(NOP) & Device Deselect
3.2.5 Row Active
3.2.6 Read Bank
3.2.7 Write Bank
3.3 Essential Functionality for DDR SDRAM
3.3.1 Burst Read Operation
3.3.2 Burst Write Operation
3.3.3 Read Interrupted by a Read
3.3.4 Read Interrupted by a Write & Burst Stop
3.3.5 Read Interrupted by a Precharge
3.3.6 Write Interrupted by a Write
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REV. 0.7 Jan. 31. 2002
256Mb C-die(x4/8) DDR SDRAM
3.3.7 Write Interrupted by a Read & DM
3.3.8 Write Interrupted by a Precharge & DM
3.3.9 Burst Stop
3.3.10 DM masking
3.3.11 Read With Auto Precharge
3.3.12 Write With Auto Precharge
3.3.13 Auto Refresh & Self Refresh
3.3.14 Power Down
4. Command Truth Table
5. Functional Truth Table
6. Absolute Maximum Rating
7. DC Operating Conditions & Specifications
7.1 DC Operating Conditions
7.2 DC Specifications
8. AC Operating Conditions & Timming Specification
8.1 AC Operating Conditions
8.2 AC Overshoot/Undershoot specification
8.2.1 Overshoot/Undershoot specification for Address and Control Pins
8.2.2 Overshoot/Undershoot specification for Data Pins
8.3 AC Timming Parameters & Specification(For DDR266/DDR200)
8.4 AC Timming Parameters & Specification(For DDR333)
9. AC Operating Test Conditions
10. Input/Output Capacitance
11. IBIS: I/V Characteristics for Input and Output Buffers
11.1 Normal strength driver
11.2 Half strength driver
Timing Diagram
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REV. 0.7 Jan. 31. 2002
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