NM93CS56 (MICROWIRE Bus Interface) 2048-Bit Serial EEPROM
with Data Protect and Sequential Read
February 2000
NM93CS56
(MICROWIRE™ Bus Interface) 2048-Bit Serial EEPROM
with Data Protect and Sequential Read
General Description
NM93CS56 is a 2048-bit CMOS non-volatile EEPROM organized
as 128 x 16-bit array. This device features MICROWIRE interface
which is a 4-wire serial bus with chipselect (CS), clock (SK), data
input (DI) and data output (DO) signals. This interface is compat-
ible to many of standard Microcontrollers and Microprocessors.
NM93CS56 offers programmable write protection to the memory
array using a special register called Protect Register. Selected
memory locations can be protected against write by programming
this Protect Register with the address of the first memory location
to be protected (all locations greater than or equal to this first
address are then protected from further change). Additionally, this
address can be “permanently locked” into the device, making all
future attempts to change data impossible. In addition this device
features “sequential read”, by which, entire memory can be read
in one cycle instead of multiple single byte read cycles. There are
10 instructions implemented on the NM93CS56, 5 of which are for
memory operations and the remaining 5 are for Protect Register
operations. This device is fabricated using Fairchild Semiconduc-
tor floating-gate CMOS process for high reliability, high endurance
and low power consumption.
“LZ” and “L” versions of NM93CS56 offer very low standby current
making them suitable for low power applications. This device is offered
in both SO and TSSOP packages for small space considerations.
Features
I
Wide V
CC
2.7V - 5.5V
I
Programmable write protection
I
Sequential register read
I
Typical active current of 200µA
10µA standby current typical
1µA standby current typical (L)
0.1µA standby current typical (LZ)
I
No Erase instruction required before Write instruction
I
Self timed write cycle
I
Device status during programming cycles
I
40 year data retention
I
Endurance: 1,000,000 data changes
I
Packages available: 8-pin SO, 8-pin DIP, 8-pin TSSOP
Functional Diagram
CS
SK
DI
INSTRUCTION
REGISTER
V
CC
INSTRUCTION
DECODER
CONTROL LOGIC
AND CLOCK
GENERATORS
PRE
PE
ADDRESS
REGISTER
PROTECT
REGISTER
COMPARATOR
AND
WRITE ENABLE
HIGH VOLTAGE
GENERATOR
AND
PROGRAM
TIMER
DECODER
EEPROM ARRAY
16
READ/WRITE AMPS
16
V
SS
DATA IN/OUT REGISTER
16 BITS
DO
DATA OUT BUFFER
© 1999 Fairchild Semiconductor Corporation
NM93CS56 Rev. F.2
1
www.fairchildsemi.com
NM93CS56 (MICROWIRE Bus Interface) 2048-Bit Serial EEPROM
with Data Protect and Sequential Read
Connection Diagram
Dual-In-Line Package (N)
8–Pin SO (M8) and 8–Pin TSSOP (MT8)
CS
SK
DI
DO
1
2
3
4
8
7
6
5
V
CC
PRE
PE
GND
Top View
Package Number
N08E, M08A and MTC08
Pin Names
CS
SK
DI
DO
GND
PE
PRE
V
CC
Chip Select
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
Program Enable
Protect Register Enable
Power Supply
Ordering Information
NM
93
CS
XX
LZ
E
XXX
Package
Letter
N
M8
MT8
None
V
E
Blank
L
LZ
56
C
CS
Interface
93
Description
8-pin DIP
8-pin SO
8-pin TSSOP
0 to 70°C
-40 to +125°C
-40 to +85°C
4.5V to 5.5V
2.7V to 5.5V
2.7V to 5.5V and
<1µA Standby Current
2048 bits
CMOS
Data protect and sequential
read
MICROWIRE
Temp. Range
Voltage Operating Range
Density
Fairchild Memory Prefix
2
NM93CS56 Rev. F.2
www.fairchildsemi.com
NM93CS56 (MICROWIRE Bus Interface) 2048-Bit Serial EEPROM
with Data Protect and Sequential Read
Absolute Maximum Ratings
(Note 1)
Ambient Storage Temperature
All Input or Output Voltages
with Respect to Ground
Lead Temperature
(Soldering, 10 sec.)
ESD rating
-65°C to +150°C
+6.5V to -0.3V
Operating Conditions
Ambient Operating Temperature
NM93CS56
NM93CS56E
NM93CS56V
Power Supply (V
CC
)
0°C to +70°C
-40°C to +85°C
-40°C to +125°C
4.5V to 5.5V
+300°C
2000V
DC and AC Electrical Characteristics
V
CC
= 4.5V to 5.5V unless otherwise specified
Symbol
I
CCA
I
CCS
I
IL
I
OL
V
IL
V
IH
V
OL1
V
OH1
V
OL2
V
OH2
f
SK
t
SKH
t
SKL
t
SKS
t
CS
t
CSS
t
PRES
t
DH
t
PES
t
DIS
t
CSH
t
PEH
t
PREH
t
DIH
t
PD
t
SV
t
DF
t
WP
Parameter
Operating Current
Standby Current
Input Leakage
Output Leakage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
SK Clock Frequency
SK High Time
SK Low Time
SK Setup Time
Minimum CS Low Time
CS Setup Time
PRE Setup Time
DO Hold Time
PE Setup Time
DI Setup Time
CS Hold Time
PE Hold Time
PRE Hold Time
DI Hold Time
Output Delay
CS to Status Valid
CS to DO in Hi-Z
Write Cycle Time
Conditions
CS = V
IH
, SK=1.0 MHz
CS = V
IL
V
IN
= 0V to V
CC
(Note 2)
Min
Max
1
50
±-1
Units
mA
µA
µA
V
V
V
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
-0.1
2
I
OL
= 2.1 mA
I
OH
= -400
µA
I
OL
= 10
µA
I
OH
= -10
µA
(Note 3)
0°C to +70°C
-40°C to +125°C
250
300
250
50
(Note 4)
250
100
50
70
50
100
0
250
50
20
2.4
0.8
V
CC
+1
0.4
0.2
V
CC
- 0.2
1
500
500
CS = V
IL
100
10
ns
ns
ns
ms
3
NM93CS56 Rev. F.2
www.fairchildsemi.com
NM93CS56 (MICROWIRE Bus Interface) 2048-Bit Serial EEPROM
with Data Protect and Sequential Read
Absolute Maximum Ratings
(Note 1)
Ambient Storage Temperature
All Input or Output Voltages
with Respect to Ground
Lead Temperature
(Soldering, 10 sec.)
ESD rating
-65°C to +150°C
+6.5V to -0.3V
Operating Conditions
Ambient Operating Temperature
NM93CS56L/LZ
NM93CS56LE/LZE
NM93CS56LV/LZV
Power Supply (V
CC
)
0°C to +70°C
-40°C to +85°C
-40°C to +125°C
2.7V to 5.5V
+300°C
2000V
DC and AC Electrical Characteristics
V
CC
= 2.7V to 5.5V unless otherwise specified
Symbol
I
CCA
I
CCS
Parameter
Operating Current
Standby Current
L
LZ (2.7V to 4.5V)
Input Leakage
Output Leakage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
SK Clock Frequency
SK High Time
SK Low Time
SK Setup Time
Minimum CS Low Time
CS Setup Time
PRE Setup Time
DO Hold Time
PE Setup Time
DI Setup Time
CS Hold Time
PE Hold Time
PRE Hold Time
DI Hold Time
Output Delay
CS to Status Valid
CS to DO in Hi-Z
Write Cycle Time
Conditions
CS = V
IH
, SK=1.0 MHz
CS = V
IL
Min
Max
1
10
1
±1
Units
mA
µA
µA
µA
V
V
KHz
µs
µs
µs
µs
µs
ns
ns
ns
µs
ns
ns
ns
µs
µs
µs
µs
ms
I
IL
I
OL
V
IL
V
IH
V
OL
V
OH
f
SK
t
SKH
t
SKL
t
SKS
t
CS
t
CSS
t
PRES
t
DH
t
PES
t
DIS
t
CSH
t
PEH
t
PREH
t
DIH
t
PD
t
SV
t
DF
t
WP
V
IN
= 0V to V
CC
(Note 2)
-0.1
0.8V
CC
I
OL
= 10µA
I
OH
= -10µA
(Note 3)
0.9V
CC
0
1
1
0.2
1
0.2
50
70
50
0.4
0
250
50
0.4
0.15V
CC
V
CC
+1
0.1V
CC
250
(Note 4)
2
1
CS = V
IL
0.4
15
Capacitance
T
A
= 25°C, f = 1 MHz (Note 5)
Symbol
C
OUT
C
IN
Note 1:
Stress above those listed under “Absolute Maximum Ratings” may cause permanent damage
to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect device reliability.
Note 2:
Typical leakage values are in the 20nA range.
Test
Output Capacitance
Input Capacitance
Typ
Max
5
5
Units
pF
pF
Note 3:
The shortest allowable SK clock period = 1/f
SK
(as shown under the f
SK
parameter). Maximum
SK clock speed (minimum SK period) is determined by the interaction of several AC parameters stated
in the datasheet. Within this SK period, both t
SKH
and t
SKL
limits must be observed. Therefore, it is not
allowable to set 1/f
SK
= t
SKHminimum
+ t
SKLminimum
for shorter SK cycle time operation.
Note 4:
CS (Chip Select) must be brought low (to V
IL
) for an interval of t
CS
in order to reset all internal
device registers (device reset) prior to beginning another opcode cycle. (This is shown in the opcode
diagram on the following page.)
AC Test Conditions
V
CC
Range
(Extended Voltage Levels)
Note 5:
This parameter is periodically sampled and not 100% tested.
V
IL
/V
IH
Input Levels
0.3V/1.8V
0.4V/2.4V
V
IL
/V
IH
Timing Level
1.0V
1.0V/2.0V
V
OL
/V
OH
Timing Level
0.8V/1.5V
0.4V/2.4V
I
OL
/I
OH
±10µA
2.1mA/-0.4mA
2.7V
≤
V
CC
≤
5.5V
(TTL Levels)
4.5V
≤
V
CC
≤
5.5V
Output Load: 1 TTL Gate (C
L
= 100 pF)
4
NM93CS56 Rev. F.2
www.fairchildsemi.com
NM93CS56 (MICROWIRE Bus Interface) 2048-Bit Serial EEPROM
with Data Protect and Sequential Read
Pin Description
Chip Select (CS)
This is an active high input pin to NM93CS56 EEPROM (the device)
and is generated by a master that is controlling the device. A high
level on this pin selects the device and a low level deselects the
device. All serial communications with the device is enabled only
when this pin is held high. However this pin cannot be permanently
tied high, as a rising edge on this signal is required to reset the
internal state-machine to accept a new cycle and a falling edge to
initiate an internal programming after a write cycle. All activity on the
SK, DI and DO pins are ignored while CS is held low.
Program Enable (PE)
This is an active high input pin to the device and is used to enable
operations, that are write in nature, to the memory array and to the
Protect register. When this pin is held high, operations that are
“write” in nature are enabled. When this pin is held low, operations
that are “write” in nature are disabled. This pin operates in
conjunction with PRE pin. Refer Table1 for functional matrix of this
pin for various operations.
Microwire Interface
A typical communication on the Microwire bus is made through the
CS, SK, DI and DO signals. To facilitate various operations on the
Memory array and on the Protect Register, a set of 10 instructions
are implemented on NM93CS56. The format of each instruction is
listed in Table 1.
Serial Clock (SK)
This is an input pin to the device and is generated by the master that
is controlling the device. This is a clock signal that synchronizes the
communication between a master and the device. All input informa-
tion (DI) to the device is latched on the rising edge of this clock input,
while output data (DO) from the device is driven from the rising edge
of this clock input. This pin is gated by CS signal.
Instruction
Each of the above 10 instructions is explained under individual
instruction descriptions.
Serial Input (DI)
This is an input pin to the device and is generated by the master
that is controlling the device. The master transfers Input informa-
tion (Start bit, Opcode bits, Array addresses and Data) serially via
this pin into the device. This Input information is latched on the
rising edge of the SCK. This pin is gated by CS signal.
Start Bit
This is a 1-bit field and is the first bit that is clocked into the device
when a Microwire cycle starts. This bit has to be “1” for a valid cycle
to begin. Any number of preceding “0” can be clocked into the
device before clocking a “1”.
Opcode
This is a 2-bit field and should immediately follow the start bit.
These two bits (along with PRE, PE signals and 2 MSB of address
field) select a particular instruction to be executed.
Serial Output (DO)
This is an output pin from the device and is used to transfer Output
data via this pin to the controlling master. Output data is serially
shifted out on this pin from the rising edge of the SCK. This pin is
active only when the device is selected.
Address Field
This is a 8-bit field and should immediately follow the Opcode bits.
In NM93CS56, only the LSB 7 bits are used for address decoding
during READ, WRITE and PRWRITE instructions. During these
three instructions (READ, WRITE and PRWRITE), the MSB is
“don’t care” (can be 0 or 1). During all other instructions (with the
exception of PRREAD), the MSB 2 bits are used to decode
instruction (along with Opcode bits, PRE and PE signals).
Protect Register Enable (PRE)
This is an active high input pin to the device and is used to
distinguish operations to memory array and operations to Protect
Register. When this pin is held low, operations to the memory
array are enabled. When this pin is held high, operations to the
Protect Register are enabled. This pin operates in conjunction
with PE pin. Refer Table1 for functional matrix of this pin for
various operations.
Data Field
This is a 16-bit field and should immediately follow the Address
bits. Only the WRITE and WRALL instructions require this field.
D15 (MSB) is clocked first and D0 (LSB) is clocked last (both
during writes as well as reads).
TABLE 1. Instruction set
Instruction
READ
WEN
WRITE
WRALL
WDS
PRREAD
PREN
PRCLEAR
PRWRITE
PRDS
Start Bit Opcode Field
1
1
1
1
1
1
1
1
1
1
10
00
01
00
00
10
00
11
01
00
X
1
X
0
0
X
1
1
X
0
A6
1
A6
1
0
X
1
1
A6
0
Address Field
A5
X
A5
X
X
X
X
1
A5
0
A4
X
A4
X
X
X
X
1
A4
0
A3
X
A3
X
X
X
X
1
A3
0
A2
X
A2
X
X
X
X
1
A2
0
A1
X
A1
X
X
X
X
1
A1
0
A0
X
A0
X
X
X
X
1
A0
0
Data Field
PRE Pin
0
0
PE Pin
X
1
1
1
X
X
1
1
1
1
D15-D0
D15-D0
0
0
0
1
1
1
1
1
5
NM93CS56 Rev. F.2
www.fairchildsemi.com
京公网安备 11010802033920号
EEWORLD
