DATA SHEET
µ
PD6124A, 6600A
4-BIT SINGLE-CHIP MICROCONTROLLER
FOR REMOTE CONTROL TRANSMISSION
MOS INTEGRATED CIRCUIT
DESCRIPTION
The
µ
PD6124A and 6600A are 4-bit single-chip microcontrollers for infrared remote controllers for TVs, VCRs,
stereos, cassette decks, air conditions, etc.
These microcontrollers consist of ROM, RAM, a 4-bit parallel-processing ALU, a programmable timer, key input/
output ports, and transmit output ports. Functioning is controlled by a program.
A one-time PROM, model
µ
PD61P24, to which a program can be written only once is also available. This one-time
PROM is ideal for evaluation of programs running in a
µ
PD6124A or 6600A, and for small-scale production of such
systems.
FEATURES
•
•
•
•
Transmitter for programmable infrared remote control-
ler
19 types of instructions
Instruction execution time: 17.6
µ
s (with 455-kHz ce-
ramic resonator)
Program memory (ROM) capacity
•
µ
PD6124A: 1002
×
10 bits
•
µ
PD6600A: 512
×
10 bits
•
•
•
•
•
•
Transmission-in-progress indication pin (S-OUT): 1
pin
Transmit carrier frequency (REM)
f
OSC
/12, f
OSC
/8
Standby operation (HALT/STOP mode)
Low power consumption
Current consumption in STOP mode (T
A
= 25°C)
Low-voltage operation
•
•
•
•
•
Data memory (RAM) capacity: 32
×
5 bits
9-bit programmable timer: 1 channel
I/O pins (K
I/O
): 8 pins
Input pins (K
I
): 4 pins
Serial input pins (S-IN): 1 pin
Caution
µ
PD6124A: V
DD
= 2.2 to 5.5 V
µ
PD6600A: V
DD
= 2.2 to 3.6 V
To use the NEC transmission format, ask NEC to supply the custom code.
Do not use R
0
when using a register as an operand of the branch instruction.
The information in this document is subject to change without notice.
Document No. U12391EJ5V0DS00 (5th edition)
(Previous No. IC-1927)
Date Published June 1997 N
Printed in Japan
The mark
shows major revised points.
©
1989
µ
PD6124A, 6600A
ORDERING INFORMATION
Part Number
Package
20-pin plastic shrink DIP (300 mil)
20-pin plastic SOP (300 mil)
20-pin plastic shrink DIP (300 mil)
20-pin plastic SOP (300 mil)
µ
PD6124ACS-XXX
µ
PD6124AGS-XXX
µ
PD6600ACS-XXX
µ
PD6600AGS-XXX
Remark
XXX indicates ROM code suffix.
PIN CONFIGURATION (TOP VIEW)
K
I/O1
1
K
I/O0
2
S-IN 3
S-OUT 4
REM 5
V
DD
6
OSC-OUT 7
OSC-IN 8
V
SS
9
AC 10
20 K
I/O2
19 K
I/O3
18 K
I/O4
17 K
I/O5
16 K
I/O6
15 K
I/O7
14 K
I0
13 K
I1
12 K
I2
11 K
I3
2
µ
PD6124A, 6600A
BLOCK DIAGRAM
ROM
D.P.
ROM
D.P.
PC(L)
PC(H)
L
H
M
P
X
ROM
(L)
Note
CNTL CNTL
(L)
(H)
32
×
5 bits
SP
ADD
DEC
M
P
X
RAM
RAM
ROM
(H)
To S-OUT
TIMER TIMER
(L)
(H)
10 bits
OSC
MOD
ALU
ACC
KEY
KEY
OUT(L) OUT(H)
KEY
IN
Watchdog
Low-
voltage
timer
detector
function
circuit
OSC-IN S-OUT REM
OSC-OUT
S-IN
K
I/O0
-K
I/O7
K
I0
-K
I3
AC
Note
ROM capacity depends on the products.
DIFFERENCES AMONG PRODUCTS
Item
ROM Capacity
RAM Capacity
I/O Pins
S-IN Pins
Current Consumption
(f
OSC
= STOP) (MAX.)
S-IN High Level Input
Current (MAX.)
Transmit Carrier Frequency
Low-voltage Detector
(Reset) Circuit
Supply Current
Package
V
DD
= 2.2 to 5.5 V
• 20-pin plastic SOP (300 mil)
• 20-pin plastic shrink DIP (300 mil)
V
DD
= 2.2 to 3.6 V
f
OSC
/12, f
OSC
/8
Provided
30
µ
A
Product Name
µ
PD6124A
1002
×
10 bits (Mark ROM)
32
×
5 bits
8 (K
I/O0
-
KI/O7
)
Provided
2
µ
A
µ
PD6600A
512
×
10 bits (Mask ROM)
3
µ
PD6124A, 6600A
1.
PROGRAM COUNTER (PC) ……… 9 BITS
10 BITS
:
µ
PD6600A
:
µ
PD6124A
The program counter (PC) is a binary counter, which holds the address information for the program memory.
Figure 1-1. Program Counter Organization
(a)
PC
8
PC
7
PC
6
PC
5
µ
PD6600A
PC
4
PC
3
PC
2
PC
1
PC
0
PC
(b)
PC
9
PC
8
PC
7
PC
6
PC
5
µ
PD6124A
PC
4
PC
3
PC
2
PC
1
PC
0
PC
Normally, the program counter contents are automatically incremented each time an instruction is executed,
according to the number of instruction bytes.
When executing a jump instruction (JMP0, JC, JF), the program counter indicates the jump destination.
Immediate data or the data memory contents are loaded to all or some bits of the PC.
When executing the call instruction (CALL0), the PC contents are incremented (+1) and saved into the stack memory.
Then, a value needed for each jump instruction will be loaded.
When executing the return instruction (RET), the stack memory contents are double incremented (+2) and loaded
into the PC.
When “all clear” is input or on reset, the PC contents are cleared to “000H”.
2.
STACK POINTER (SP) ……… 2 BITS
This 2-bit register holds the start address information for the stack area. The stack area is shared with the data
memory.
The SP contents are incremented, when the call instruction (CALL0) is executed. They are decremented, when the
return instruction (RET) is executed.
The stack pointer is cleared to “00B” after reset or “all clear” is input, and indicates the highest address FH for the
data memory as the stack area.
The figure below shows the relationship for the stack pointer and the data memory area.
Data memory
R
C
R
D
R
E
R
F
(SP)
11B
10B
01B
00B
If the stack pointer overflows or underflows, it is determined that the CPU overflows, and the PC internal reset signal
will be generated.
4
µ
PD6124A, 6600A
3.
PROGRAM MEMORY (ROM) ……… 512 STEPS
×
10 BITS :
µ
PD6600A
1002 STEPS
×
10 BITS :
µ
PD6124A
The program memory (ROM) is configured in 10 bits steps. It is addressed by the program counter.
Program and table data are stored in the program memory.
Figure 3-1. Program Memory Map
(a)
000H
0FFH
100H
1FFH
µ
PD6600A
000H
0FFH
100H
1FFH
200H
2FFH
300H
3E9H
3EAH
3FFH
(b)
µ
PD6124A
Test program
area
4.
DATA MEMORY (RAM) ……… 32 WORDS
×
5 BITS
The data memory is a RAM of 32 words
×
5 bits. The data memory stores processing data. In some cases, the
data memory is processed in 8-bit units. R
0
may be used as the data pointer for the ROM.
After power application, the RAM will be undefined. The RAM retains the previous data on reset.
Figure 4-1. Data Memory Organization
1
0
R
0
.
.
.
R
B
R
C
.
.
.
R
F
SP–3
SP–2
SP–1
SP–0
Caution
Avoid using the RAM areas R
D
, R
E
, and R
F
in a CALL routine as much as possible because these areas
are also used as stack memory areas (to prevent program hang-up in case the value of the SP is
destroyed due to some reason such as noise).
When using these RAM areas as general-purpose RAM areas, be sure to include stack pointer
checking in the main routine.
5
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