QL3012-0PFN100I datasheet, PDF

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QL3012-0PFN100I: DescriptionField Programmable Gate Array, 320 CLBs, 12000 Gates, 225MHz, 320-Cell, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, LEAD FREE, MO-136, TQFP-100; CategoryProgrammable logic devices Programmable logic; File Size886KB，49 Pages; ManufacturerQuickLogic Corporation; Websitehttps://www.quicklogic.com; Environmental Compliance

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QL3012-0PFN100I Overview

Field Programmable Gate Array, 320 CLBs, 12000 Gates, 225MHz, 320-Cell, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, LEAD FREE, MO-136, TQFP-100

QL3012-0PFN100I Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	QuickLogic Corporation
Parts packaging code	QFP
package instruction	LFQFP, QFP100,.63SQ,20
Contacts	100
Reach Compliance Code	compliant
Other features	CAN ALSO BE OPERATED AT 5.0V
maximum clock frequency	225 MHz
Combined latency of CLB-Max	6.08 ns
JESD-30 code	S-PQFP-G100
JESD-609 code	e3
length	14 mm
Humidity sensitivity level	3
Configurable number of logic blocks	320
Equivalent number of gates	12000
Number of entries	118
Number of logical units	320
Output times	110
Number of terminals	100
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	320 CLBS, 12000 GATES
Package body material	PLASTIC/EPOXY
encapsulated code	LFQFP
Encapsulate equivalent code	QFP100,.63SQ,20
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	260
power supply	3.3,3.3/5 V
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum supply voltage	3.6 V
Minimum supply voltage	3 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Matte Tin (Sn)
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	40
width	14 mm

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pASIC 3 FPGA Family Data Sheet

••••••

Up to 60,000 Usable PLD Gate pASIC 3 FPGA Combining High

Performance and High Density

Device Highlights

High Performance & High Density

• Up to 60,000 usable PLD gates with up to

316 I/Os

• 300 MHz 16-bit counters, 400 MHz datapaths

• 0.35 µm four-layer metal non-volatile CMOS

process for smallest die sizes

Up to Eight Low-Skew Distributed

Networks

• Two array clock/control networks are available to

the logic cell flip-flop; clock, set, and reset inputs

— each can be driven by an input-only pin

• Up to six global clock/control networks are

available to the logic cell; F1, clock, set, and reset

inputs and the data input, I/O register clock,

reset, and enable inputs as well as the output

enable control — each can be driven by an input-

only pin, I/O pin, any logic cell output, or I/O cell

feedback

Easy to Use/Fast Development

Cycles

• 100% routable with 100% utilization and

complete pin-out stability

• Variable-grain logic cells provide high

performance and 100% utilization

• Comprehensive design tools include high quality

Verilog/VHDL synthesis

High Performance

• Input + logic cell + output total delays under 6 ns

• Data path speeds over 400 MHz

• Counter speeds over 300 MHz

Figure 1:

Up to 1,584

pASIC 3 Logic Cells

Advanced I/O Capabilities

• Interfaces with 3.3 V and 5.0 V devices

• PCI compliant with 3.3 V and 5.0 V buses

for -1/-2/-3/-4 speed grades

• Full JTAG boundary scan

• I/O cells with individually controlled registered

input path and output enables

Up to 316 I/O Pins

• Up to 308 bidirectional input/output pins,

PCI-compliant for 5.0 V and 3.3 V buses for

-1/-2/-3/-4 speed grades

• Up to eight high-drive input/distributed network

pins

www.quicklogic.com

•

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