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8T39S10NLGI8

Description
VFQFPN-48, Reel
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size1MB,44 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance  
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8T39S10NLGI8 Overview

VFQFPN-48, Reel

8T39S10NLGI8 Parametric

Parameter NameAttribute value
Brand NameIntegrated Device Technology
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerIDT (Integrated Device Technology)
Parts packaging codeVFQFPN
package instructionVFQFPN-48
Contacts48
Manufacturer packaging codeNLG48P1
Reach Compliance Codecompliant
ECCN codeEAR99
Other featuresALSO OPERATES TA 3.3 V SUPPLY
JESD-30 codeS-XQCC-N48
JESD-609 codee3
length7 mm
Humidity sensitivity level3
Number of terminals48
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Maximum output clock frequency2000 MHz
Package body materialUNSPECIFIED
encapsulated codeHVQCCN
Package shapeSQUARE
Package formCHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)260
Master clock/crystal nominal frequency40 MHz
Maximum seat height0.9 mm
Maximum supply voltage2.625 V
Minimum supply voltage2.375 V
Nominal supply voltage2.5 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceMatte Tin (Sn)
Terminal formNO LEAD
Terminal pitch0.5 mm
Terminal locationQUAD
Maximum time at peak reflow temperatureNOT SPECIFIED
width7 mm
uPs/uCs/peripheral integrated circuit typeCLOCK GENERATOR, OTHER
Crystal or Differential to Differential
Clock Fanout Buffer
General Description
The IDT8T39S10I is a high-performance clock fanout buffer. The
input clock can be selected from two differential inputs or one crystal
input. The internal oscillator circuit is automatically disabled if the
crystal input is not selected. The crystal pin can be driven by
single-ended clock when crystal is bypassed.The selected signal is
distributed to ten differential outputs which can be configured as
LVPECL, LVDS or HSCL outputs. In addition, an LVCMOS output is
provided. All outputs can be disabled into a high-impedance state.
The device is designed for signal fanout of high-frequency, low
phase-noise clock and data signal. The outputs are at a defined level
when inputs are open circuit or tied to ground. It is designed to
operate from a 3.3V or 2.5V core power supply, and either a 3.3V or
2.5V output operating supply.
IDT8T39S10I
DATASHEET
Features
Two differential reference clock input pairs
Differential input pairs can accept the following differential input
levels: LVPECL, LVDS, HCSL
Crystal Oscillator Interface
Crystal input frequency range: 10MHz to 40MHz
Maximum Output Frequency
LVPECL - 2GHz
LVDS
- 2GHz
HCSL
- 250MHz
LVCMOS - 250MHz
Two banks, each has five differential output pairs that can be
configured as LVPECL or LVDS or HCSL
One single-ended reference output with synchronous enable to
avoid clock glitch
Output skew: (Bank A and Bank B at the same output level)
70ps (max)
Part-to-part skew: 250ps (max)
Additive RMS phase jitter: 0.153ps (typical)
Supply voltage modes:
V
DD
/V
DDO
3.3V/3.3V
3.3V/2.5V
2.5V/2.5V
-40°C to 85°C ambient operating temperature
Lead-free (RoHS 6) packaging
IDT8T39S10NLGI REVISION A MARCH 18. 2014
1
©2014 Integrated Device Technology, Inc.

8T39S10NLGI8 Related Products

8T39S10NLGI8 8T39S10NLGI
Description VFQFPN-48, Reel VFQFPN-48, Tray
Brand Name Integrated Device Technology Integrated Device Technology
Is it lead-free? Lead free Lead free
Is it Rohs certified? conform to conform to
Maker IDT (Integrated Device Technology) IDT (Integrated Device Technology)
Parts packaging code VFQFPN VFQFPN
package instruction VFQFPN-48 VFQFPN-48
Contacts 48 48
Manufacturer packaging code NLG48P1 NLG48P1
Reach Compliance Code compliant compliant
ECCN code EAR99 EAR99
Other features ALSO OPERATES TA 3.3 V SUPPLY ALSO OPERATES TA 3.3 V SUPPLY
JESD-30 code S-XQCC-N48 S-XQCC-N48
JESD-609 code e3 e3
length 7 mm 7 mm
Humidity sensitivity level 3 3
Number of terminals 48 48
Maximum operating temperature 85 °C 85 °C
Minimum operating temperature -40 °C -40 °C
Maximum output clock frequency 2000 MHz 2000 MHz
Package body material UNSPECIFIED UNSPECIFIED
encapsulated code HVQCCN HVQCCN
Package shape SQUARE SQUARE
Package form CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius) 260 260
Master clock/crystal nominal frequency 40 MHz 40 MHz
Maximum seat height 0.9 mm 0.9 mm
Maximum supply voltage 2.625 V 2.625 V
Minimum supply voltage 2.375 V 2.375 V
Nominal supply voltage 2.5 V 2.5 V
surface mount YES YES
technology CMOS CMOS
Temperature level INDUSTRIAL INDUSTRIAL
Terminal surface Matte Tin (Sn) Matte Tin (Sn)
Terminal form NO LEAD NO LEAD
Terminal pitch 0.5 mm 0.5 mm
Terminal location QUAD QUAD
Maximum time at peak reflow temperature NOT SPECIFIED NOT SPECIFIED
width 7 mm 7 mm
uPs/uCs/peripheral integrated circuit type CLOCK GENERATOR, OTHER CLOCK GENERATOR, OTHER
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