HY5DU283222AFP-33 datasheet, PDF

Datasheet> All Categories > storage> storage> HY5DU283222AFP-33

HY5DU283222AFP-33: DescriptionDDR DRAM, 4MX32, 0.6ns, CMOS, PBGA144, 12 X 12 MM, 0.80 MM PITCH, LEAD FREE, FBGA-144; Categorystorage storage; File Size244KB，31 Pages; ManufacturerSK Hynix; Websitehttp://www.hynix.com/eng/; Environmental Compliance

Download Datasheet Parametric Compare View All

HY5DU283222AFP-33 Overview

DDR DRAM, 4MX32, 0.6ns, CMOS, PBGA144, 12 X 12 MM, 0.80 MM PITCH, LEAD FREE, FBGA-144

HY5DU283222AFP-33 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	SK Hynix
Parts packaging code	BGA
package instruction	TFBGA, BGA144,12X12,32
Contacts	144
Reach Compliance Code	unknown
ECCN code	EAR99
access mode	FOUR BANK PAGE BURST
Maximum access time	0.6 ns
Other features	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	300 MHz
I/O type	COMMON
interleaved burst length	2,4,8
JESD-30 code	S-PBGA-B144
JESD-609 code	e1
length	12 mm
memory density	134217728 bit
Memory IC Type	DDR DRAM
memory width	32
Number of functions	1
Number of ports	1
Number of terminals	144
word count	4194304 words
character code	4000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	4MX32
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	TFBGA
Encapsulate equivalent code	BGA144,12X12,32
Package shape	SQUARE
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	260
power supply	2.5 V
Certification status	Not Qualified
refresh cycle	4096
Maximum seat height	1.2 mm
self refresh	YES
Continuous burst length	2,4,8
Maximum standby current	0.025 A
Maximum slew rate	0.7 mA
Maximum supply voltage (Vsup)	2.625 V
Minimum supply voltage (Vsup)	2.2 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Silver/Copper (Sn/Ag/Cu)
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	20
width	12 mm

Preview

Download Datasheet

View All

HY5DU283222AF(P)

128M(4Mx32) GDDR SDRAM

HY5DU283222AF(P)

This document is a general product description and is subject to change without notice. Hynix Electronics does not assume any respon-

sibility for use of circuits described. No patent licenses are implied.

Rev. 0.8/ Jun. 2004

HY5DU283222AF(P)

PIN DESCRIPTION

CK, /CK

TYPE

Input

DESCRIPTION

Clock: CK and /CK are differential clock inputs. All address and control input signals are

sampled on the crossing of the positive edge of CK and negative edge of /CK. Output

(read) data is referenced to the crossings of CK and /CK (both directions of crossing).

Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, and

device input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER

DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row

ACTIVE in any bank). CKE is synchronous for POWER DOWN entry and exit, and for SELF

REFRESH entry. CKE is asynchronous for SELF REFRESH exit, and for output disable. CKE

must be maintained high throughout READ and WRITE accesses. Input buffers, excluding

CK, /CK and CKE are disabled during POWER DOWN. Input buffers, excluding CKE are

disabled during SELF REFRESH. CKE is an SSTL_2 input, but will detect an LVCMOS LOW

level after Vdd is applied.

Chip Select : Enables or disables all inputs except CK, /CK, CKE, DQS and DM. All com-

mands are masked when CS is registered high. CS provides for external bank selection on

systems with multiple banks. CS is considered part of the command code.

Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, Read, Write or PRE-

CHARGE command is being applied.

Address Inputs: Provide the row address for ACTIVE commands, and the column address

and AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the

memory array in the respective bank. A8 is sampled during a precharge command to

determine whether the PRECHARGE applies to one bank (A8 LOW) or all banks (A8

HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1. The

address inputs also provide the op code during a MODE REGISTER SET command. BA0

and BA1 define which mode register is loaded during the MODE REGISTER SET command

(MRS or EMRS).

Command Inputs: /RAS, /CAS and /WE (along with /CS) define the command being

entered.

Input Data Mask: DM(0~3) is an input mask signal for write data. Input data is masked

when DM is sampled HIGH along with that input data during a WRITE access. DM is sam-

pled on both edges of DQS. Although DM pins are input only, the DM loading matches the

DQ and DQS loading. DM0 corresponds to the data on DQ0-Q7; DM1 corresponds to the

data on DQ8-Q15; DM2 corresponds to the data on DQ16-Q23; DM3 corresponds to the

data on DQ24-Q31.

Data Strobe: Output with read data, input with write data. Edge aligned with read data,

centered in write data. Used to capture write data. DQS0 corresponds to the data on

DQ0-Q7; DQS1 corresponds to the data on DQ8-Q15; DQS2 corresponds to the data on

DQ16-Q23; DQS3 corresponds to the data on DQ24-Q31

Data input / output pin : Data Bus

Power supply for internal circuits and input buffers.

Power supply for output buffers for noise immunity.

Reference voltage for inputs for SSTL interface.

No connection.

CKE

Input

/CS

Input

BA0, BA1

Input

A0 ~ A11

Input

/RAS, /CAS, /WE

Input

DM0 ~ DM3

Input

DQS0 ~ DQS3

I/O

DQ0 ~ DQ31

DDQ

SSQ

REF

I/O

Supply

Rev. 0.8 / Jun. 2004

HY5DU283222AFP-33 Related Products

	HY5DU283222AFP-33	HY5DU283222AFP-5	HY5DU283222AFP-36	HY5DU283222AFP-4
Description	DDR DRAM, 4MX32, 0.6ns, CMOS, PBGA144, 12 X 12 MM, 0.80 MM PITCH, LEAD FREE, FBGA-144	DDR DRAM, 4MX32, 0.6ns, CMOS, PBGA144, 12 X 12 MM, 0.80 MM PITCH, LEAD FREE, FBGA-144	DDR DRAM, 4MX32, 0.6ns, CMOS, PBGA144, 12 X 12 MM, 0.80 MM PITCH, LEAD FREE, FBGA-144	DDR DRAM, 4MX32, 0.6ns, CMOS, PBGA144, 12 X 12 MM, 0.80 MM PITCH, LEAD FREE, FBGA-144
Is it Rohs certified?	conform to	conform to	conform to	conform to
Parts packaging code	BGA	BGA	BGA	BGA
package instruction	TFBGA, BGA144,12X12,32	TFBGA, BGA144,12X12,32	TFBGA, BGA144,12X12,32	TFBGA, BGA144,12X12,32
Contacts	144	144	144	144
Reach Compliance Code	unknown	unknown	unknown	unknown
ECCN code	EAR99	EAR99	EAR99	EAR99
access mode	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST
Maximum access time	0.6 ns	0.6 ns	0.6 ns	0.6 ns
Other features	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	300 MHz	200 MHz	275 MHz	250 MHz
I/O type	COMMON	COMMON	COMMON	COMMON
interleaved burst length	2,4,8	2,4,8	2,4,8	2,4,8
JESD-30 code	S-PBGA-B144	S-PBGA-B144	S-PBGA-B144	S-PBGA-B144
JESD-609 code	e1	e1	e1	e1
length	12 mm	12 mm	12 mm	12 mm
memory density	134217728 bit	134217728 bit	134217728 bit	134217728 bit
Memory IC Type	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM
memory width	32	32	32	32
Number of functions	1	1	1	1
Number of ports	1	1	1	1
Number of terminals	144	144	144	144
word count	4194304 words	4194304 words	4194304 words	4194304 words
character code	4000000	4000000	4000000	4000000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	70 °C	70 °C	70 °C	70 °C
organize	4MX32	4MX32	4MX32	4MX32
Output characteristics	3-STATE	3-STATE	3-STATE	3-STATE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TFBGA	TFBGA	TFBGA	TFBGA
Encapsulate equivalent code	BGA144,12X12,32	BGA144,12X12,32	BGA144,12X12,32	BGA144,12X12,32
Package shape	SQUARE	SQUARE	SQUARE	SQUARE
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	260	260	260	260
power supply	2.5 V	2.5 V	2.5 V	2.5 V
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified
refresh cycle	4096	4096	4096	4096
Maximum seat height	1.2 mm	1.2 mm	1.2 mm	1.2 mm
self refresh	YES	YES	YES	YES
Continuous burst length	2,4,8	2,4,8	2,4,8	2,4,8
Maximum standby current	0.025 A	0.025 A	0.025 A	0.025 A
Maximum slew rate	0.7 mA	0.6 mA	0.6 mA	0.6 mA
Maximum supply voltage (Vsup)	2.625 V	2.625 V	2.625 V	2.625 V
Minimum supply voltage (Vsup)	2.2 V	2.2 V	2.2 V	2.2 V
Nominal supply voltage (Vsup)	2.5 V	2.5 V	2.5 V	2.5 V
surface mount	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal surface	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Silver/Copper (Sn/Ag/Cu)
Terminal form	BALL	BALL	BALL	BALL
Terminal pitch	0.8 mm	0.8 mm	0.8 mm	0.8 mm
Terminal location	BOTTOM	BOTTOM	BOTTOM	BOTTOM
Maximum time at peak reflow temperature	20	20	20	20
width	12 mm	12 mm	12 mm	12 mm
Maker	SK Hynix	-	SK Hynix	SK Hynix

Recommended Resources

Audio power amplifier circuit using MAX9789A and MAX9713 chips

Quad op amp LM324

LED fuse blown indication circuit

Electromechanical control single-sided Class A power amplifier circuit

TEM-0302 schematic circuit

Separately excited switching integrated regulated power supply composed of BG602

Shortcut: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 SA SB SC SD SE SF SG SH SI SJ SK SL SM SN SO SP SQ SR SS ST SU SV SW SX SY SZ T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 TA TB TC TD TE TF TG TH TI TJ TK TL TM TN TO TP TQ TR TS TT TU TV TW TX TY TZ U0 U1 U2 U3 U4 U6 U7 U8 UA UB UC UD UE UF UG UH UI UJ UK UL UM UN UP UQ UR US UT UU UV UW UX UZ V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VA VB VC VD VE VF VG VH VI VJ VK VL VM VN VO VP VQ VR VS VT VU VV VW VX VY VZ W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 WA WB WC WD WE WF WG WH WI WJ WK WL WM WN WO WP WR WS WT WU WV WW WY X0 X1 X2 X3 X4 X5 X7 X8 X9 XA XB XC XD XE XF XG XH XK XL XM XN XO XP XQ XR XS XT XU XV XW XX XY XZ Y0 Y1 Y2 Y4 Y5 Y6 Y9 YA YB YC YD YE YF YG YH YK YL YM YN YP YQ YR YS YT YX Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z8 ZA ZB ZC ZD ZE ZF ZG ZH ZJ ZL ZM ZN ZP ZR ZS ZT ZU ZV ZW ZX ZY

Popular Components