UPD485505G-25 datasheet, PDF - EEWORLD Datasheet

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UPD485505G-25: DescriptionLINE BUFFER 5K-WORD BY 8-BIT; File Size116KB，20 Pages; ManufacturerNEC ( Renesas ); Websitehttps://www2.renesas.cn/zh-cn/

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UPD485505G-25 Overview

LINE BUFFER 5K-WORD BY 8-BIT

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DATA SHEET

MOS INTEGRATED CIRCUIT

PD485505

LINE BUFFER

5K-WORD BY 8-BIT

Description

The

PD485505 is a 5,048 words by 8 bits high speed FIFO (First In First Out) line buffer. Its CMOS static circuitry

provides high speed access and low power consumption.

The

PD485505 can be used for one line delay and time axis conversion in high speed facsimile machines and

digital copiers.

Moreover, the

PD485505 can execute read and write operations independently on an asynchronous basis. Thus

the

PD485505 is suitable as a buffer for data transfer between units with different transfer rates and as a buffer for

the synchronization of multiple input signals. There are three versions, E, K, P, and L. This data sheet can be applied

to the version P and L. These versions operate with different specifications. Each version is identified with its lot

number (refer to

7. Example of Stamping).

Features

• 5,048 words by 8 bits

• Asynchronous read/write operations available

• Variable length delay bits; 21 to 5,048 bits (Cycle time: 25 ns)

15 to 5,048 bits (Cycle time: 35 ns)

• Power supply voltage V

= 5.0 V

0.5 V

• Suitable for sampling one line of A3 size paper (16 dots/mm)

• All input/output TTL compatible

• 3-state output

• Full static operation; data hold time = infinity

Ordering Information

Part Number

R/W Cycle Time

25 ns

35 ns

Package

24-pin plastic SOP

(11.43 mm (450))

PD485505G-25

PD485505G-35

The information in this document is subject to change without notice. Before using this document, please

confirm that this is the latest version.

Not all devices/types available in every country. Please check with local NEC representative for availability

and additional information.

Document No. M10059EJ7V0DSJ1 (7th edition)

Date Published December 2000 N CP(K)

Printed in Japan

The mark

shows major revised points.

1994,1996

PD485505

2. Operation Mode

PD485505 is a synchronous memory. All signals are strobed at the rising edge of the clock (RCK, WCK).

For this reason, setup time and hold time are specified for the rising edge of the clock (RCK, WCK).

2.1 Write Cycle

When the WE input is enabled (“L” level), a write cycle is executed in synchronization with the WCK clock

input.

The data inputs are strobed by the rising edge of the clock at the end of a cycle so that read data after a one-

line (5,048 bits) delay and write data can be processed with the same clock. Refer to Write Cycle Timing Chart.

When WE is disabled (“H” level) in a write cycle, the write operation is not performed during the cycle which

the WCK rising edge is in the WE = “H” level (t

WEW

). The WCK does not increment the write address pointer

at this time.

Unless inhibited by WE, the internal write address will automatically wrap around from 5,047 to 0 and begin

incrementing again.

2.2 Read Cycle

When the RE input is enabled (“L” level), a read cycle is executed in synchronization with the RCK clock input

and data is output after t

. Refer to Read Cycle Timing Chart.

When RE is disabled (“H” level) in a read cycle, the read operation is not performed during the cycle which

the RCK rising edge is in the RE = “H” level (t

REW

). The RCK does not increment the read address pointer at

this time.

2.3 Write Reset Cycle/Read Reset Cycle

After power up, the

PD485505 requires the initialization of internal circuits because the read and write

address pointers are not defined at that time.

It is necessary to satisfy setup requirements and hold times as measured from the rising edge of WCK and

RCK, and then input the RSTW and RSTR signals to initialize the circuit.

Write and read reset cycles can be executed at any time and the address pointer returns zero. Refer to Write

Reset Cycle Timing Chart, Read Reset Cycle Timing Chart.

Remark

Write and read reset cycles can be executed at any time and do not depend on the state of RE or WE.

Data Sheet M10059EJ7V0DS00

UPD485505G-25 Related Products

	UPD485505G-25	D485505G	UPD485505G-35	UPD485505
Description	LINE BUFFER 5K-WORD BY 8-BIT	LINE BUFFER 5K-WORD BY 8-BIT	LINE BUFFER 5K-WORD BY 8-BIT	LINE BUFFER 5K-WORD BY 8-BIT

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