KMM377S1620DT3-GH datasheet, PDF

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KMM377S1620DT3-GH: DescriptionSynchronous DRAM Module, 16MX72, 6ns, CMOS; Categorystorage storage; File Size215KB，11 Pages; ManufacturerSAMSUNG; Websitehttp://www.samsung.com/Products/Semiconductor/

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KMM377S1620DT3-GH Overview

Synchronous DRAM Module, 16MX72, 6ns, CMOS

KMM377S1620DT3-GH Parametric

Parameter Name	Attribute value
Maker	SAMSUNG
package instruction	DIMM, DIMM168
Reach Compliance Code	unknown
ECCN code	EAR99
access mode	FOUR BANK PAGE BURST
Maximum access time	6 ns
Other features	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	100 MHz
I/O type	COMMON
JESD-30 code	R-XDMA-N168
memory density	1207959552 bit
Memory IC Type	SYNCHRONOUS DRAM MODULE
memory width	72
Number of functions	1
Number of ports	1
Number of terminals	168
word count	16777216 words
character code	16000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	16MX72
Output characteristics	3-STATE
Package body material	UNSPECIFIED
encapsulated code	DIMM
Encapsulate equivalent code	DIMM168
Package shape	RECTANGULAR
Package form	MICROELECTRONIC ASSEMBLY
power supply	3.3 V
Certification status	Not Qualified
refresh cycle	4096
self refresh	YES
Maximum standby current	0.02 A
Maximum slew rate	2.75 mA
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	NO LEAD
Terminal pitch	1.27 mm
Terminal location	DUAL

KMM377S1620DT3-GH Preview

KMM377S1620DT3

Revision History

Revision 0.0 (June 2, 1999)

PC100 Registered DIMM

• Changed tRDL from 1CLK to 2CLK in OPERATING AC PARAMETER.

• Skip ICC4 value of CL=2 in DC characteristics in datasheet.

• Define a new parameter of tDAL( 2CLK +20ns), Last data in to Active delay in OPERATING AC PARAMETER.

• Eliminated FREQUENCY vs.PARAMETER RELATIONSHIP TABLE.

• Symbol Change Notice

Before

Input leakage current (inputs)

Input leakage current (I/O pins)

Output open @ DC characteristic table

After

Input leakage current

Output open @ DC characteristic table

•

Test Condition in

DC CHARACTERISTIC Change Notice

Symbol

CC2P ,

CC3P

CC2N ,

CC3N

CC4

Before

CKE

≤

(max), t

= 15ns

CKE

≥

(min), CS

≥

(min), t

= 15ns

Input signals are changed one time during 30ns

2 Banks activated

After

CKE

≤

(max), t

= 10ns

CKE

≥

(min), CS

≥

(min), t

= 10ns

Input signals are changed one time during 20ns

4 Banks activated

Revision 0.1 (July 5, 1999)

• Added Notes @OPERATING AC PARAMETER

Notes : 5. For -H/L, tRDL=1CLK and tDAL=1CLK+20ns is also supported .

SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + 20ns.

• Redefind feedback capacitor value to Cb, variable value @ Functional Block Diagram.

Rev. 0.1 July 1999

KMM377S1620DT3

KMM377S1620DT3 SDRAM DIMM (Intel 1.2 ver Base)

PC100 Registered DIMM

16Mx72 SDRAM DIMM with PLL & Register based on 16Mx4, 4Banks, 4K Ref., 3.3V Synchronous DRAMs with SPD

GENERAL DESCRIPTION

The Samsung KMM377S1620DT3 is a 16M bit x 72 Synchro-

nous Dynamic RAM high density memory module. The Sam-

sung KMM377S1620DT3 consists of eighteen CMOS 16Mx4

bit Synchronous DRAMs in TSOP-II 400mil packages, three

18-bits Drive ICs for input control signal, one PLL in 24-pin

TSSOP package for clock and one 2K EEPROM in 8-pin

TSSOP package for Serial Presence Detect on a 168-pin

glass-epoxy substrate. Two 0.22uF and one 0.0022uF decou-

pling capacitors are mounted on the printed circuit board in

parallel for each SDRAM. The KMM377S1620DT3 is a Dual In-

line Memory Module and is intented for mounting into 168-pin

edge connector sockets.

Synchronous design allows precise cycle control with the use

of system clock. I/O transactions are possible on every clock

cycle. Range of operating frequencies, programmable laten-

cies allows the same device to be useful for a variety of high

bandwidth, high performance memory system applications.

FEATURE

• Performance range

Part No.

KMM377S1620DT3-GH

KMM377S1620DT3-GL

•

Max Freq. (Speed)

100MHz (10ns @ CL=2)

100MHz (10ns @ CL=3)

Burst mode operation

Auto & self refresh capability (4096 Cycles/64ms)

LVTTL compatible inputs and outputs

Single 3.3V

0.3V power supply

MRS cycle with address key programs

Latency (Access from column address)

Burst length (1, 2, 4, 8 & Full page)

Data scramble (Sequential & Interleave)

• All inputs are sampled at the positive going edge of the

system clock

• Serial presence detect with EEPROM

• PCB :

Height (1,700mil),

double sided component

PIN CONFIGURATIONS (Front side/back side)

Front

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

CB0

CB1

DQM0

Front

DQ18

DQ19

DQ20

REF

*CKE1

DQ21

DQ22

DQ23

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

*CLK2

**SDA

**SCL

Back

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

Back

DQM5

*CS1

RAS

BA0

A11

*CLK1

*A12

CKE0

*CS3

DQM6

DQM7

*A13

CB6

CB7

DQ48

DQ49

Back

29 DQM1 57

CS0

38 A10/AP 66

BA1

42 CLK0 70

CS2

46 DQM2 74

47 DQM3 75

CB2

CB3

55 DQ16 83

56 DQ17 84

86 DQ32

87 DQ33

88 DQ34

89 DQ35

91 DQ36

92 DQ37

93 DQ38

94 DQ39

95 DQ40

97 DQ41

98 DQ42

99 DQ43

100 DQ44

101 DQ45

102 V

103 DQ46

104 DQ47

105 CB4

106 CB5

107

108

109

110 V

111 CAS

112 DQM4

141 DQ50

142 DQ51

143 V

144 DQ52

145

146 *V

REF

147 REGE

148

149 DQ53

150 DQ54

151 DQ55

152

153 DQ56

154 DQ57

155 DQ58

156 DQ59

157 V

158 DQ60

159 DQ61

160 DQ62

161 DQ63

162

163 *CLK3

164

165 **SA0

166 **SA1

167 **SA2

168 V

.PIN

NAMES

Pin Name

A0 ~ A11

BA0 ~ BA1

DQ0 ~ DQ63

CB0 ~ CB7

CLK0

CKE0

CS0, CS2

RAS

CAS

DQM0 ~ 7

REF

REGE

SDA

SCL

SA0 ~ 2

Function

Address input (Multiplexed)

Select bank

Data input/output

Check bit (Data-in/data-out)

Clock input

Clock enable input

Chip select input

Row address strobe

Colume address strobe

Write enable

DQM

Power supply (3.3V)

Ground

Power supply for reference

Serial data I/O

Serial clock

Address in EEPROM

Don′t use

No connection

Write protection

* These pins are not used in this module.

These pins should be NC in the system

which does not support SPD.

SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.

Rev. 0.1 July 1999

KMM377S1620DT3

PIN CONFIGURATION DESCRIPTION

CLK

Name

System clock

Chip select

PC100 Registered DIMM

Input Function

Active on the positive going edge to sample all inputs.

Disables or enables device operation by masking or enabling all inputs except

CLK, CKE and DQM

Masks system clock to freeze operation from the next clock cycle.

CKE should be enabled at least one cycle prior to new command.

Disable input buffers for power down in standby.

CKE should be enabled 1CLK+tss prior to valid command.

Row/column addresses are multiplexed on the same pins.

Row address : RA0 ~ RA11, Column address : CA0 ~ CA9

Selects bank to be activated during row address latch time.

Selects bank for read/write during column address latch time.

Latches row addresses on the positive going edge of the CLK with RAS low.

Enables row access & precharge.

Latches column addresses on the positive going edge of the CLK with CAS low.

Enables column access.

Enables write operation and row precharge.

Latches data in starting from CAS, WE active.

Makes data output Hi-Z, t

SHZ

after the clock and masks the output.

Blocks data input when DQM active. (Byte masking)

The device operates in the transparent mode when REGE is low. When REGE is high,

the device operates in the registered mode. In registered mode, the Address and con-

trol inputs are latched if CLK is held at a high or low logic level. the inputs are stored in

the latch/flip-flop on the rising edge of CLK. REGE is tied to V

through 10K ohm

Resistor on PCB. So if REGE of module is floating, this module will be operated as reg-

istered mode.

Data inputs/outputs are multiplexed on the same pins.

Check bits for ECC.

WP pin is connected to V

through 47KΩ Resistor.

When WP is "high", EEPROM Programming will be inhibited and the entire memory will

be write-protected.

Power and ground for the input buffers and the core logic.

CKE

Clock enable

A0 ~ A11

BA0 ~ BA1

RAS

CAS

DQM0 ~ 7

Address

Bank select address

Row address strobe

Column address strobe

Write enable

Data input/output mask

REGE

DQ0 ~ 63

CB0 ~ 7

Data input/output

Check bit

Write protection

Power supply/ground

Rev. 0.1 July 1999

KMM377S1620DT3

FUNCTIONAL BLOCK DIAGRAM

PCLK0

BCS0

CKE0

A0~B

A11,B

BA0,B

BA1,B

RAS,B

CAS,B

BDQM0

DQ0~3

10Ω

CLK

CKE

Add,CTL

DQM

DQ0~3

CLK

CKE

Add,CTL

DQM

DQ0~3

10Ω

PCLK1

CLK

CKE

Add,CTL

DQM

DQ0~3

CLK

CKE

Add,CTL

DQM

DQ0~3

PC100 Registered DIMM

CKE0

BDQM4

DQ32~35

10Ω

CLK

CKE

Add,CTL

DQM

DQ0~3

CLK

CKE

Add,CTL

DQM

DQ0~3

CLK

CKE

Add,CTL

DQM

DQ0~3

CLK

CKE

Add,CTL

DQM

DQ0~3

CLK

CKE

Add,CTL

DQM

DQ0~3

CLK

CKE

Add,CTL

DQM

DQ0~3

10Ω

DQ36~39

D10

DQ4~7

BDQM5

DQ40~43

10Ω

D11

BDQM1

DQ8~11

10Ω

PCLK2

10Ω

DQ44~47

D12

DQ12~15

10Ω

CB0~3

10Ω

PCLK3

BCS2

CLK

CKE

Add,CTL

DQM

DQ0~3

10Ω

D13

CB4~7

DQ16~19

10Ω

PCLK4

CLK

CKE

Add,CTL

DQM

DQ0~3

CLK

CKE

Add,CTL

DQM

DQ0~3

CLK

CKE

Add,CTL

DQM

DQ0~3

DQ48~51

10Ω

D14

BDQM6

DQ52~55

10Ω

BDQM2

DQ20~23

10Ω

CLK

CKE

Add,CTL

DQM

DQ0~3

CLK

CKE

Add,CTL

DQM

DQ0~3

D15

DQ56~59

10Ω

D16

DQ24~27

10Ω

PCLK5

A0~B

A11,B

BA1,B

RAS,B

CAS,B

BDQM3

DQ28~31

10Ω

,BA0

10kΩ

PCLK6

REGE

,BA1

CS2

CKE0

DQM2,3,6,7

RAS,CAS,WE

CS0

DQM0,1,4,5

CLK

CKE

Add,CTL

DQM

DQ0~3

BDQM7

DQ60~63

10Ω

CLK

CKE

Add,CTL

DQM

DQ0~3

D17

SN74ALVC162835

AGND

AVCL

BA0

IY0

IY1

IY2

IY3

IY4

PCLK0

PCLK1

PCLK2

PCLK3

PCLK4

PCLK5

PCLK6

CDC2509

10Ω

11.

BA1

11.

BA1

BCS2

CKE0

BDQM2,3,6,7

RAS, B

CAS, B

RAS, B

CAS, B

BCS0

BDQM0,1,4,5

CLK0

12pF

CLK

FIBIN

2Y0

2Y1

SN74ALVC162835

FBOUT

* Note

1. Unused clock termination : 10Ω and 12pF

2. The actual values of

will depend upon the PLL chosen.

SN74ALVC162835

Serial PD

SCL

47KΩ

SDA

SA0 SA1 SA2

Rev. 0.1 July 1999

KMM377S1620DT3

PC100 Registered DIMM

STANDARD TIMING DIAGRAM WITH PLL & REGISTER (CL=2, BL=4)

Control Signal(RAS,CAS,WE)

REG

OUT

*1. Register Input

CLK

RAS

CAS

*2. Register Output

RAS

CAS

*3. SDRAM

CAS latency(refer to *1)

=2CLK+1CLK

tSAC

tRAC(refer to *1)

1CLK

tRAC(refer to *2)

Qa0

Qa1

Qa2

Qa3

Db0

Db1

Db2

Db3

CAS latency(refer to *2)

=2CLK

tRDL

Row Active

Read

Command

Precharge

Command

Row Active

Write

Command

Precharge

Command

td, tr = Delay of register (74ALVC162835)

Notes :

1. In case of module timing, command cycles delayed 1CLK with respect to external input timing at the address and input signal

because of the buffering in register (74ALVC162835). Therefore, Input/Output signals of read/write function should be

issued 1CLK earlier as compared to Unbuffered DIMMs.

2. D

is to be issued 1clock after write command in external timing because D

is issued directly to module.

: Don

′t

care

Rev. 0.1 July 1999

More (Only the first 5 pages are displayed. Please Download Datasheet to view the full content.) >

KMM377S1620DT3-GH Related Products

	KMM377S1620DT3-GH	KMM377S1620DT3-GL
Description	Synchronous DRAM Module, 16MX72, 6ns, CMOS	Synchronous DRAM Module, 16MX72, 6ns, CMOS
Maker	SAMSUNG	SAMSUNG
package instruction	DIMM, DIMM168	DIMM, DIMM168
Reach Compliance Code	unknown	unknown
ECCN code	EAR99	EAR99
access mode	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST
Maximum access time	6 ns	6 ns
Other features	AUTO/SELF REFRESH	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	100 MHz	100 MHz
I/O type	COMMON	COMMON
JESD-30 code	R-XDMA-N168	R-XDMA-N168
memory density	1207959552 bit	1207959552 bit
Memory IC Type	SYNCHRONOUS DRAM MODULE	SYNCHRONOUS DRAM MODULE
memory width	72	72
Number of functions	1	1
Number of ports	1	1
Number of terminals	168	168
word count	16777216 words	16777216 words
character code	16000000	16000000
Operating mode	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	70 °C	70 °C
organize	16MX72	16MX72
Output characteristics	3-STATE	3-STATE
Package body material	UNSPECIFIED	UNSPECIFIED
encapsulated code	DIMM	DIMM
Encapsulate equivalent code	DIMM168	DIMM168
Package shape	RECTANGULAR	RECTANGULAR
Package form	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY
power supply	3.3 V	3.3 V
Certification status	Not Qualified	Not Qualified
refresh cycle	4096	4096
self refresh	YES	YES
Maximum standby current	0.02 A	0.02 A
Maximum slew rate	2.75 mA	2.75 mA
Maximum supply voltage (Vsup)	3.6 V	3.6 V
Minimum supply voltage (Vsup)	3 V	3 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V
surface mount	NO	NO
technology	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL
Terminal form	NO LEAD	NO LEAD
Terminal pitch	1.27 mm	1.27 mm
Terminal location	DUAL	DUAL

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