application
INFO
available
UCC1809-1/-2
UCC2809-1/-2
UCC3809-1/-2
Economy Primary Side Controller
FEATURES
•
User Programmable Soft Start With
Active Low Shutdown
•
User Programmable Maximum Duty
Cycle
•
Accessible 5V Reference
•
Undervoltage Lockout
•
Operation to 1MHz
•
0.4A Source/0.8A Sink FET Driver
•
Low 100µA Startup Current
DESCRIPTION
The UCC3809 family of BCDMOS economy low power integrated circuits
contains all the control and drive circuitry required for off-line and isolated
DC-to-DC fixed frequency current mode switching power supplies with
minimal external parts count. Internally implemented circuits include
undervoltage lockout featuring startup current less than 100µA, a user ac-
cessible voltage reference, logic to ensure latched operation, a PWM com-
parator, and a totem pole output stage to sink or source peak current. The
output stage, suitable for driving N-Channel MOSFETs, is low in the off
state.
Oscillator frequency and maximum duty cycle are programmed with two
resistors and a capacitor. The UCC3809 family also features full cycle soft
start.
The family has UVLO thresholds and hysteresis levels for off-line and
DC-to-DC systems as shown in the table to the left.
PART
TURN ON
TURN OFF
NUMBER THRESHOLD THRESHOLD
UCCX809-1
10V
8V
UCCX809-2
15V
8V
The UCC3809 and the UCC2809 are offered in the 8 pin SOIC (D), PDIP
(N), TSSOP (PW), and MSOP (P) packages. The small TSSOP and
MSOP packages make the device ideal for applications where board
space and height are at a premium.
TYPICAL APPLICATION DIAGRAM
R
START
V
IN
FB
1V
1
1V
NOISE
FILTER
FEEDBACK
REF
+5V
SS
5V
REF
8
C
REF
V
OUT
6µA
2
CURRENT
SENSE
SLOPE
COMP
0.5V
C
SS
DISABLE
UVLO
VDD
7
15/8V
10/8V
17.5V
C
VDD
RT1
3
OSC
4
C
T
PWM
LATCH
CLK
R
Q
S
6
OUT
RT2
GND
5
V
REF
UDG-99036
SLUS166A - NOVEMBER 1999
UCC1809-1/-2
UCC2809-1/-2
UCC3809-1/-2
ABSOLUTE MAXIMUM RATINGS*
VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19V
I
VDD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25mA
I
OUT
(tpw < 1µs and Duty Cycle < 10%) . . . . . . . . –0.4A to 0.8A
RT1, RT2, SS . . . . . . . . . . . . . . . . . . . . . . –0.3V to REF + 0.3V
I
REF
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –15mA
Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . –55°C to +150°C
Lead Temperature (Soldering, 10 sec.) . . . . . . . . . . . . . +300°C
CONNECTION DIAGRAM
SOIC-8, DIL-8 (Top View)
D, N and J Packages
* Values beyond which damage may occur.
All voltages are with respect to ground unless otherwise stated.
Currents are positive into, negative out of the specified termi-
nal. Consult Packaging Section of Databook for thermal limita-
tions and considerations of packages.
TSSOP-8 (Top View)
PW Package
1
2
3
4
FB
SS
RT1
RT2
REF
VDD
OUT
GND
8
7
6
5
MSOP-8 (Top View)
P Package
1
2
3
4
FB
SS
RT1
RT2
REF
VDD
OUT
GND
8
7
6
5
ORDERING INFORMATION
UCC1809-X
UCC2809-X
UCC3809-X
Temperature Range Available Packages
–55°C to +125°C
J
–40°C to +85°C
N, D, P, PW
0°C to +70°C
N, D, P, PW
UCC
809
–
ELECTRICAL CHARACTERISTICS
: Unless otherwise specified, VDD = 12V. T
A
= T
J
.
PARAMETER
Supply Section
VDD Clamp
I
VDD
I
VDD
Starting
Undervoltage Lockout Section
Start Threshold (UCCx809-1)
UVLO Hysteresis (UCCx809-1)
Start Threshold (UCCx809-2)
UVLO Hysteresis (UCCx809-2)
Voltage Reference Section
Output Voltage
Line Regulation
Load Regulation
Comparator Section
I
FB
Comparator Threshold
OUT Propagation Delay (No Load)
I
VDD
= 10mA
No Load
TEST CONDITIONS
MIN
16
TYP
17.5
600
MAX
19
900
100
10.4
15.6
UNIT
V
µA
µA
V
V
V
V
V
mV
mV
nA
V
ns
9.4
1.65
14.0
6.2
I
REF
= 0mA
VDD = 10V to 15V
I
REF
= 0mA to 5mA
Output Off
0.9
V
FB
= 0.8V to 1.2V at T
R
= 10ns
4.75
5
2
2
–100
0.95
50
5.25
1
100
2
UCC1809-1/-2
UCC2809-1/-2
UCC3809-1/-2
ELECTRICAL CHARACTERISTICS
: Unless otherwise specified, VDD = 12V. T
A
= T
J
.
PARAMETER
Soft Start Section
I
SS
V
SS
Low
Shutdown Threshold
Oscillator Section
Frequency
Frequency Change with Voltage
C
T
Peak Voltage
C
T
Valley Voltage
C
T
Peak to Peak Voltage
Output Section
Output V
SAT
Low
Output V
SAT
High
Output Low Voltage During UVLO
Minimum Duty Cycle
Maximum Duty Cycle
Rise Time
Fall Time
TEST CONDITIONS
VDD = 16V, V
SS
= 0V; –40°C to +85°C
VDD = 16V, V
SS
= 0V;
<
–40°C;
>+85°C
VDD = 7.5V, I
SS
= 200µA
MIN
–4.9
–4.0
0.44
RT1 = 10k, RT2 = 4.32k, CT = 820pF
VDD = 10V to 15V
90
TYP
–7.0
–7.0
0.48
100
0.1
3.33
1.67
1.67
0.8
0.8
0
70
35
18
MAX
–9.1
–10.0
0.2
0.52
110
UNIT
µA
µA
V
V
kHz
%/V
V
V
V
V
V
V
%
%
ns
ns
1.54
I
OUT
= 80mA (dc)
I
OUT
= –40mA (dc), VDD – OUT
I
OUT
= 20mA (dc)
V
FB
= 2V
C
OUT
= 1nF
C
OUT
= 1nF
1.80
1.5
1.5
1.5
PIN DESCRIPTIONS
FB:
This pin is the summing node for current sense
feedback, voltage sense feedback (by optocoupler) and
slope compensation. Slope compensation is derived
from the rising voltage at the timing capacitor and can be
buffered with an external small signal NPN transistor.
External high frequency filter capacitance applied from
this node to GND is discharged by an internal 250Ω on
resistance NMOS FET during PWM off time and offers
effective leading edge blanking set by the RC time
constant of the feedback resistance from current sense
resistor to FB input and the high frequency filter
capacitor capacitance at this node to GND.
GND:
Reference ground and power ground for all
functions.
OUT:
This pin is the high current power driver output. A
minimum series gate resistor of 3.9 is recommended to
limit the gate drive current when operating with high bias
voltages.
REF:
The internal 5V reference output. This reference is
buffered and is available on the REF pin. REF should be
bypassed with a 0.47µF ceramic capacitor.
RT1:
This pin connects to timing resistor RT1 and
controls the positive ramp time of the internal oscillator
(Tr = 0.74
•
(C
T
+ 27pF)
•
RT1). The positive threshold
of the internal oscillator is sensed through inactive timing
resistor RT2 which connects to pin RT2 and timing
capacitor C
T
.
3
RT2:
This pin connects to timing resistor RT2 and
controls the negative ramp time of the internal oscillator
(Tf = 0.74
•
(C
T
+ 27pF)
•
RT2). The negative threshold
of the internal oscillator is sensed through inactive timing
resistor RT1 which connects to pin RT1 and timing
capacitor C
T
.
SS:
This pin serves two functions. The soft start timing
capacitor connects to SS and is charged by an internal
6µA current source. Under normal soft start SS is
discharged to at least 0.4V and then ramps positive to
1V during which time the output driver is held low. As SS
charges from 1V to 2V soft start is implemented by an
increasing output duty cycle. If SS is taken below 0.5V,
the output driver is inhibited and held low. The user
accessible 5V voltage reference also goes low and I
VDD
< 100µA.
VDD:
The power input connection for this device. This
pin is shunt regulated at 17.5V which is sufficiently below
the voltage rating of the DMOS output driver stage. VDD
should be bypassed with a 1µF ceramic capacitor.
+V
OUT
H11AV1
5
C13
0.1µF
R15
10K
C14
470pF
R17
12.1K
1%
1
R14
750
APPLICATION INFORMATION
4
U3
U4
TL431
2
+VIN
R13
1.1K
D3
SF24
T1
80µH
1
3
C15
0.015µF
R9
2K
3W
C10
0.22µF
2
U2
MBR2535CTL
R19
5.1K
3W
R16
12.1K
1%
C3
1µF
R5
470
R12
27K
UCC3809
1
R11
680
5:1
R10
10
Q3
IRF640
C8
1µF
C9
0.1µF
C7
0.47µF
2
3
4
U1
R6
1K
RT2
5
GND
RT1
6
OUT
SS
7
VDD
FB
8
REF
Q2
2N2907A
D4
1N5240
C2
150µF
PGND1
C16
330µF
6.3V
C17
330µF
6.3V
C18
330µF
6.3V
C19
330µF
6.3V
C1
150µF
TP1
–V
OUT
ON/OFF
R4
6.19K
R20
5.62K
R3
12.1K
R1
5.1k
Q1
2N2222A
Q4
2N2222A
C6
330pF
R18
3.01K
D1
5231B
C22
0.1µF
D2
1N5245
R7
15K
R2
1.1K
C4
0.01µF
R8
0.15
3W
C5
1nF
–VIN
PGND1
UDG-99179
Figure 1. Isolated 50W flyback converter utilizing the UCC3809. The switching frequency is 70kHz, Vin = -32V
to -72V, Vout = +5V, Iout = 0A to 10A
4
UCC1809-1/-2
UCC2809-1/-2
UCC3809-1/-2
UCC1809-1/-2
UCC2809-1/-2
UCC3809-1/-2
APPLICATION INFORMATION (cont.)
The Typical Application Diagram shows an isolated
flyback converter utilizing the UCC3809. Note that the
capacitors C
REF
and C
VDD
are local decoupling capaci-
tors for the reference and IC input voltage, respectively.
Both capacitors should be low ESR and ESL ceramic,
placed as close to the IC pins as possible, and returned
directly to the ground pin of the chip for best stability.
REF provides the internal bias to many of the IC func-
tions and C
REF
should be at least 0.47µF to prevent REF
from drooping.
FB Pin
The basic premise of the UCC3809 is that the voltage
sense feedback signal originates from an optocoupler
that is modulated by an external error amplifier located
on the secondary side. This signal is summed with the
current sense signal and any slope compensation at the
FB pin and compared to a 1V threshold, as shown in the
Typical Application Diagram. Crossing this 1V threshold
resets the PWM latch and modulates the output driver
on-time much like the current sense comparator used in
the UC3842. In the absence of a FB signal, the output
will follow the programmed maximum on-time of the os-
cillator.
When adding slope compensation, it is important to use
a small capacitor to AC couple the oscillator waveform
before summing this signal into the FB pin. By correctly
selecting the emitter resistor of the optocoupler, the volt-
age sense signal can force the FB node to exceed the
1V threshold when the output that is being compared ex-
ceeds a desired level. Doing so drives the UCC3809 to
zero percent duty cycle.
Oscillator
The following equation sets the oscillator frequency:
5.0V reference) sensed through RT1. The R input to the
oscillator latch, R(OSC), is also level sensitive and resets
the CLK signal low when CT crosses the 1.67V thresh-
old, turning off Q2 and turning on Q1, initiating another
charging cycle.
Figure 3 shows the waveforms associated with the oscil-
lator latch and the PWM latch (shown in the Typical Ap-
plication Diagram). A high CLK signal not only initiates a
discharge cycle for CT, it also turns on the internal
NMOS FET on the FB pin causing any external capaci-
tance used for leading edge blanking connected to this
pin to be discharged to ground. By discharging any ex-
ternal capacitor completely to ground during the external
switch’s off-time, the noise immunity of the converter is
enhanced allowing the user to design in smaller RC com-
ponents for leading edge blanking. A high CLK signal
also sets the level sensitive S input of the PWM latch,
S(PWM), high, resulting in a high output, Q(PWM), as
shown in Figure 3. This Q(PWM) signal will remain high
until a reset signal, R(PWM) is received. A high R(PWM)
signal results from the FB signal crossing the 1V thresh-
old, or during soft start or if the SS pin is disabled.
Assuming the UVLO threshold is satisfied, the OUT sig-
nal of the IC will be high as long as Q(PWM) is high and
S(PWM), also referred to as CLK, is low. The OUT sig-
nal will be dominated by the FB signal as long as the FB
signal trips the 1V threshold while CLK is low. If the FB
signal does not cross the 1V threshold while CLK is low,
the OUT signal will be dominated by the maximum duty
cycle programmed by the user. Figure 3 illustrates the
various waveforms for a design set up for a maximum
duty cycle of 70%.
F
OSC
=
[
0.74
•
(
CT
+
27
pF
)
•
(
RT
1
+
RT
2
)
]
D
MAX
=
0.74
•
RT
1
•
(
CT
+
27
pF
)
•
F
OSC
−
1
V
REF
Q1
3
3.33V
RT1
4
1.67V
RT2
Q2
R
OSCILLATOR
LATCH
OSC
S
Q
CLK
Referring to Figure 2 and the waveforms in Figure 3,
when Q1is on, CT charges via the R
DS(on)
of Q1 and
RT1. During this charging process, the voltage of CT is
sensed through RT2. The S input of the oscillator latch,
S(OSC), is level sensitive, so crossing the upper thresh-
old (set at 2/3 VREF or 3.33V for a typical 5.0V refer-
ence) sets the Q output (CLK signal) of the oscillator
latch high. A high CLK signal results in turning off Q1
and turning on Q2. CT now discharges through RT2 and
the R
DS(on)
of Q2. CT discharges from 3.33V to the
lower threshold (set at 1/3 VREF or 1.67V for a typical
CT
UDG-97195
Figure 2. UCC3809 oscillator.
5
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