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P4C1256-25FC

Description
Standard SRAM, 32KX8, 25ns, CMOS, CDFP28, CERAMIC, FP-28
Categorystorage    storage   
File Size1MB,16 Pages
ManufacturerPyramid Semiconductor Corporation
Websitehttp://www.pyramidsemiconductor.com/
Download Datasheet Parametric View All

P4C1256-25FC Overview

Standard SRAM, 32KX8, 25ns, CMOS, CDFP28, CERAMIC, FP-28

P4C1256-25FC Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerPyramid Semiconductor Corporation
Parts packaging codeDFP
package instructionCERAMIC, FP-28
Contacts28
Reach Compliance Codecompliant
ECCN codeEAR99
Maximum access time25 ns
JESD-30 codeR-CDFP-F28
memory density262144 bit
Memory IC TypeSTANDARD SRAM
memory width8
Number of functions1
Number of terminals28
word count32768 words
character code32000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize32KX8
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeDFP
Package shapeRECTANGULAR
Package formFLATPACK
Parallel/SerialPARALLEL
Certification statusNot Qualified
Maximum seat height2.286 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal formFLAT
Terminal pitch1.27 mm
Terminal locationDUAL
width9.017 mm
P4C1256
HIGH SPEED 32K x 8
STATIC CMOS RAM
FEATURES
High Speed (Equal Access and Cycle Times)
– 12/15/20/25/35 ns (Commercial)
– 15/20/25/35/45 ns (Industrial)
– 20/25/35/45/55/70 ns (Military)
Low Power
Single 5V±10% Power Supply
Easy Memory Expansion Using
CE
and
OE
Inputs
Common Data I/O
Three-State Outputs
Fully TTL Compatible Inputs and Outputs
Advanced CMOS Technology
Fast t
OE
Automatic Power Down
Packages
– 28-Pin 300 mil DIP, SOJ, TSOP
– 28-Pin 300 mil Ceramic DIP
– 28-Pin 600 mil Plastic and Ceramic DIP
– 28-Pin CERPACK
– 28-Pin Solder Seal Flat Pack
– 28-Pin SOP
– 28-Pin LCC (350 mil x 550 mil)
– 32-Pin LCC (450 mil x 550 mil)
DESCRIPTIOn
The P4C1256 is a 262,144-bit high-speed CMOS static
RAM organized as 32K x 8. The CMOS memory requires
no clocks or refreshing, and has equal access and cycle
times. Inputs are fully TTL-compatible. The RAM operates
from a single 5V±10% tolerance power supply.
Access times as fast as 12 nanoseconds permit greatly
enhanced system operating speeds. CMOS is utilized to
reduce power consumption to a low level. The P4C1256
is a member of a family of PACE RAM™ products offering
fast access times.
The P4C1256 devices provides asynchronous operation
with matching access and cycle times. Memory locations
are specified on address pins A
0
to A
14
. Reading is accom-
plished by device selection (CE) and output enabling (OE)
while write enable (WE) remains HIGH. By presenting the
address under these conditions, the data in the addressed
memory location is presented on the data input/output pins.
The input/output pins stay in the HIGH Z state when either
CE
or
OE
is HIGH or
WE
is LOW.
Package options for the P4C1256 include 28-pin DIP, SOJ,
and TSOP packages. For military temperature range,
Ceramic DIP and LCC packages are available.
FUnCTIOnAL BLOCK DIAgRAM
PIn COnFIgURATIOnS
DIP (P5, P6, C5, C5-1, D5-1, D5-2), SOJ (J5), SOP (S11-1, S11-3)
CERPACK (F4, FS-5) SIMILAR
LCC and TSOP configurations at end of datasheet
Document #
SRAM119
REV I
Revised July 2010
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